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Data Sheet May, 2006
ORCA(R) Series 4 FPGAs
Introduction
Built on the Series 4 reconfigurable embedded system-on-a-chip (SoC) architecture, Lattice introduces its new family of generic Field-Programmable Gate Arrays (FPGAs). The high-performance and highly versatile architecture brings a new dimension to bringing network system designs to market in less time than ever before. This new device family offers many new features and architectural enhancements not available in any earlier FPGA generations. Bringing together highly flexible SRAM-based programmable logic, powerful system features, a rich hierarchy of routing and interconnect resources, and meeting multiple interface standards, the Series 4 FPGA accommodates the most complex and high-performance intellectual property (IP) network designs.

Traditional I/O selections: -- LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os. -- Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. -- Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. -- Two slew rates supported (fast and slew-limited). -- Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and zero hold time. -- Fast open-drain drive capability. -- Capability to register 3-state enable signal. -- Off-chip clock drive capability. -- Two-input function generator in output path. New programmable high-speed I/O: -- Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, and IV), ZBT, and DDR. -- Double-ended: LDVS, bused-LVDS, and LVPECL. Programmable (on/off) internal parallel termination (100 ) also supported for these I/Os.
Programmable Features
High-performance platform design: -- 0.16 m 7-level metal technology. -- Internal performance of >250 MHz. -- I/O performance of >420 MHz. -- Meets multiple I/O interface standards. -- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
Table 1. ORCA Series 4--Available FPGA Logic Device OR4E02 OR4E04 OR4E06 Rows 26 36 46 Columns 24 36 44 PFUs 624 1,296 2,024 User I/O 405 466 466 LUTs 4,992 10,368 16,192 EBR Blocks 8 12 16 EBR Bits (K) 74 111 148 Usable* Gates (K) 201--397 333--643 471--899
* The embedded system bus and MPI are not included in the above gate counts. The System Gate ranges are derived from the following: minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs. Note: Devices are not pinout compatible with ORCA Series 2/3.
(c) 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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or4e_05
ORCA Series 4 FPGAs
Data Sheet May, 2006
Table of Contents
Contents Page Contents Page
Introduction ................................................................ 1 Programmable Features ............................................ 1 System Features ....................................................... 4 Product Description ................................................... 5 Architecture Overview ..........................................5 Programmable Logic Cells ........................................ 6 Programmable Function Unit ...............................7 Look-Up Table Operating Modes .......................10 Supplemental Logic and Interconnect Cell ........20 PLC Latches/Flip-Flops ......................................24 Embedded Block RAM (EBR) .................................. 26 EBR Features ....................................................26 Routing Resources .................................................. 31 Clock Distribution Network ...................................... 31 Global Primary Clock Nets .................................31 Secondary Clock and Control Nets ....................31 Secondary Edge Clock Nets and Fast Edge Clock Nets ...................................31 Cycle Stealing ....................................................32 Programmable Input/Output Cells (PIC) .................. 32 Programmable I/O ..............................................32 Inputs .................................................................35 Outputs ..............................................................36 I/O Banks and Groups ....................................... 37 Special Function Blocks .......................................... 39 Single Function Blocks .......................................47 Microprocessor Interface (MPI) ............................... 49 Embedded System Bus (ESB) ...........................49 Phase-Locked Loops (PLLs) ................................... 53 FPGA States of Operation ....................................... 56 Initialization ........................................................56 Power Supply Sequencing .................................57 Configuration ......................................................57 Start-Up ..............................................................57 Reconfiguration ..................................................61 Partial Reconfiguration .......................................61 Other Configuration Options ..............................61 Configuration Data Format .................................61 Using ispLEVER to Generate Configuration RAM Data ...............................61 Configuration Data Frame ..................................62 Bit Stream Error Checking .................................64 FPGA Configuration Modes ..................................... 64 Master Parallel Mode .........................................65 Master Serial Mode ............................................66 Asynchronous Peripheral Mode .........................67 Microprocessor Interface Mode ..........................68 Slave Serial Mode ..............................................72 Slave Parallel Mode ...........................................72 Daisy-Chaining ...................................................73 Daisy-Chaining with Boundary-Scan ..................74 Absolute Maximum Ratings ..................................... 75 Recommended Operating Conditions ................75 Electrical Characteristics ......................................... 76 Power Estimation ..................................................... 77 Estimating Power Dissipation .................................. 77 Timing Characteristics ............................................. 78 Configuration Timing ..........................................92 Readback Timing ............................................ 100 Pin Information ...................................................... 101 Pin Descriptions .............................................. 101 Package Compatibility ..................................... 105 352-Pin PBGA Pinout ...................................... 107 416-Pin BGAM Pinout ..................................... 116 680-Pin PBGAM Pinout ................................... 126 Package Thermal Characteristics Summary ......... 142 JA ................................................................. 142 JC ................................................................. 142 JC ................................................................. 143 JB ................................................................. 143 Package Thermal Characteristics .......................... 144 Package Coplanarity ............................................. 144 Heat Sink Vendors for BGA Packages .................. 144 Package Parasitics ................................................ 145 Package Outline Diagrams .................................... 146 Terms and Definitions ..................................... 146 352-Pin PBGA ................................................. 147 416-Pin PBGAM .............................................. 148 680-Pin PBGAM .............................................. 149 Ordering Information .............................................. 150
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Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Features (continued)
New capability to (de)multiplex I/O signals: -- New double data rate on both input and output at rates up to 350 MHz (700 MHz effective rate). -- New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). Enhanced twin-quad programmable function unit (PFU): -- Eight 16-bit look-up tables (LUTs) per PFU. -- Nine user registers per PFU, one following each LUT and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. -- New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. -- New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 to 1 MUX, new 8 to 1 MUX, and ripple mode arithmetic functions in the same PFU. -- 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. -- Soft-wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed. -- Flexible fast access to PFU inputs from routing. -- Fast-carry logic and routing to all four adjacent PFUs for nibble-, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. SLIC provides eight 3-statable buffers, up to 10-bit decoder, and PALTM-like and-or-invert (AOI) in each programmable logic cell.
Improved built-in clock management with programmable phase-locked loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x possible. New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be configured as: -- 1-512 x 18 (quad-port, two read/two write) with optional built in arbitration. -- 1-256 x 36 (dual-port, one read/one write). -- 1-1K x 9 (dual-port, one read/one write). -- 2-512 x 9 (dual-port, one read/one write for each). -- 2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). -- Supports joining of RAM blocks. -- Two 16 x 8-bit content addressable memory (CAM) support. -- FIFO 512 x 18, 256 x 36, 1K x 9 or dual 512 x 9. -- Constant multiply (8 x 16 or 16 x 8). -- Dual-variable multiply (8 x 8). Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-in system registers that act as the control and status center for the device. Built-in testability: -- Full boundary scan (IEEE (R) 1149.1 and Draft 1149.2 joint test access group (JTAG)). -- Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. -- TS_ALL testability function to 3-state all I/O pins. -- New temperature sensing diode. New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also enables compliance with many setup/hold and clock-to-out I/O specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers.

Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
System Features

PCI local bus compliant. Improved PowerPC (R)/PowerQUICCMPC860 and PowerPC II MPC8260 high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space provided. New embedded AMBATM specification 2.0 AHB system bus (ARMTM processor) facilitates communication among the microprocessor interface, configuration logic, embedded block RAM, FPGA logic, and embedded standard cell blocks. New network PLLs meet ITU-T G.811 specifications and provide clock conditioning for DS-1/E-1 and STS-3/STM-1 applications. Variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. Internal, 3-state, bidirectional buses with simple control provided by the SLIC. New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for OR4E04). New local clock routing structures allow creation of localized clock trees. Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved setup/hold and clock to out performance.
New double-data rate (DDR) and zero-bus turnaround (ZBT) memory interfaces support the latest high-speed memory interfaces. New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal logic. Meets universal test and operations PHY interface for ATM (UTOPIA) Levels 1, 2, and 3. Also meets proposed specifications for UTOPIA level 4, POSPHY Level 3 (2.5 Gbits/s), and POS-PHY 4 (10 Gbits/s) interface standards for packet-over-SONET as defined by the Saturn Group. ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthesis, simulation, and timing analysis.

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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
provide the global routing and clocking elements. Each PLC contains a PFU, SLIC, local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. The Series 4 architecture integrates macrocell blocks of memory known as EBR. The blocks run horizontally across the PLC array and provide flexible memory functionality. Large blocks of 512x18 quad-port RAM compliment the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM, typically without the use of PFUs for implementation. System-level functions such as a microprocessor interface, PLLs, embedded system bus elements (located in the corners of the array), the routing resources, and configuration RAM are also integrated elements of the architecture. For Series 4 FPSCs, all PIO buffers and logic are replaced by the embedded logic core on the side of the device. The four PLLs on the right side of the device (two in the upper right corner and two in the lower right corner) are removed and the embedded system bus extends into the FPSC section.
Product Description
Architecture Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages, and speed grades. The hierarchical architecture of the logic, clocks, routing, RAM and system level blocks create a seamless merge of FPGA and ASIC designs. Modular hardware and software technologies enable system-on-chip integration with True Plug and Play design implementation. The architecture consists of four basic elements: programmable logic cells (PLCs), programmable input/output cells (PIOs), embedded block RAMs (EBRs), and system-level features. A high-level block diagram is shown in Figure 1. These elements are interconnected with a rich routing fabric of both global and local wires. An array of PLCs and its associated resources are surrounded by common interface blocks (CIBs) which provide an abundant interface to the adjacent PIOs or system blocks. Routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. PICS provide the logical interface to the PIOs which provide the boundary interface off and onto the device. Also the interquad routing blocks (hIQ, vIQ) separate the quadrants of the PLC array and
Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
Product Description (continued)
EMBEDDED BLOCK RAM EMBEDDED MICROPROCESSOR INTERFACE (MPI)
HIGH-SPEED I/Os
SYSTEM BUS
REPLACED BY EMBEDDED IP CORE FOR FPSCs
CLOCK PINS (ALL 4 SIDES) PFU
SLIC PLC PIO PIC
FPGA/SYSTEM BUS INTERFACE
PLLs (ALL 4 CORNERS)
Note: For FPSCs, all I/Os and the four PLLs on the right side of the device are replaced with the embedded core.
5-7536(F)a
Figure 1. Series 4 Top Level Diagram
Programmable Logic Cells
The PLCs are arranged in an array of rows and columns. The location of a PLC is indicated by its row and column so that a PLC in the second row and the third column is R2C3. The array of actual PLCs for every device begins with R3C2 in all Series 4 generic FPGAs. PIOs are located on all four sides of the FPGA. Every group of four PIOs on the device edge have an associated PIC. The PLC consists of a PFU, SLIC, and routing resources. Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional FF that may be used independently or with arithmetic functions. The PFU is the main logic element of the PLC, containing elements for both combinatorial and sequential logic. Combinatorial logic is done in LUTs located in the PFU. The PFU can be used in different modes to meet different logic requirements. The LUTs twin-quad architecture provides a configurable medium-/large-grain architecture that can be used to implement from one to eight independent combinatorial logic functions or a large number of complex logic functions using multiple LUTs. The flexibility of the LUT to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count per PFU while increasing system speed. The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently. Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32x4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. 6 Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Figure 2 and Figure 3 show high-level and detailed views of the ports in the PFU, respectively. The eight sets of LUT inputs are labeled as K0 through K7 with each of the four inputs to each LUT having a suffix of _x, where x is a number from 0 to 3. There are four F5 inputs labeled A through D. These are used for additional LUT inputs for 5- and 6-input LUTs or as a selector for multiplexing two 4-input LUTs. Four adjacent LUT4s can also be multiplexed together with a 4 to 1 MUX to create a 6-input LUT. The eight direct data inputs to the latches/FFs are labeled as DIN[7:0]. Registered LUT outputs are shown as Q[7:0], and combinatorial LUT outputs are labeled as F[7:0]. The PFU implements combinatorial logic in the LUTs and sequential logic in the latches/FFs. The LUTs are static random access memory (SRAM) and can be used for read/write or ROM. Each latch/FF can accept data from its associated LUT. Alternatively, the latches/FFs can accept direct data from DIN[7:0], eliminating the LUT delay if no combinatorial function is needed. Additionally, the CIN input can be used as a direct data source for the ninth FF. The LUT outputs can bypass the latches/FFs, which reduces the delay out of the PFU. It is possible to use the LUTs and latches/FFs more or less independently, allowing, for instance, a comparator function in the LUTs simultaneously with a shift register in the FFs.
Programmable Logic Cells (continued)
The LUTs can be programmed to operate in one of three modes: combinatorial, ripple, or memory. In combinatorial mode, the LUTs can realize any 4-, 5-, or 6-input logic function and many multilevel logic functions using ORCA's SWL connections. In ripple mode, the high-speed carry logic is used for arithmetic functions, comparator functions, or enhanced data path functions. In memory mode, the LUTs can be used as a 32x4 synchronous read/write or ROM, in either singleor dual-port mode. The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU outputs make fast, True 3-state buses possible within the FPGA.
Programmable Function Unit
The PFUs are used for logic. Each PFU has 53 external inputs and 20 outputs and can operate in several modes. The functionality of the inputs and outputs depends on the operating mode. The PFU uses 36 data input lines for the LUTs, eight data input lines for the latches/FFs, eight control inputs (CLK[1:0], CE[1:0], LSR[1:0], SEL[1:0]), and a carry input (CIN) for fast arithmetic functions and generalpurpose data input for the ninth FF. There are eight combinatorial data outputs (one from each LUT), eight latched/registered outputs (one from each latch/FF), a carry-out (COUT), and a registered carry-out (REGCOUT) that comes from the ninth FF. The carry-out signals are used principally for fast arithmetic functions. There are also two dedicated F6 mode outputs which are for the 6-input LUT function and 8 to 1 MUX.
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ORCA Series 4 FPGAs
Data Sheet May, 2006
Programmable Logic Cells (continued)
F5D K7_0 K7_1 K7_2 K7_3 K6_0 K6_1 K6_2 K6_3 K5_0 K5_1 K5_2 K5_3 K4_0 K4_1 K4_2 K4_3 F5C DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIN F5B K3_0 K3_1 K3_2 K3_3 K2_0 K2_1 K2_2 K2_3 K1_0 K1_1 K1_2 K1_3 K0_0 K0_1 K0_2 K0_3 F5A LSR[0:1] CLK[0:1] CE[0:1] SEL[0:1] F7 F6 F5 F4 F3 F2 F1 F0
LUT603 LUT647
PROGRAMMABLE FUNCTION UNIT (PFU)
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 COUT REGCOUT
5-5752(F)a
Figure 2. PFU Ports The PFU can be configured to operate in four modes: logic mode, half-logic mode, ripple mode, and memory (RAM/ROM) mode. In addition, ripple mode has four submodes and RAM mode can be used in either a single- or dual-port memory fashion. These submodes of operation are discussed in the following sections.
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
FSDMUX F5D K7_0 K7_1 K7_2 K7_3 K6_0 K6_1 K6_2 K6_3 K5_0 K5_1 K5_2 K5_3 K4_0 K4_1 K4_2 K4_3 F5C 0 SR1MODEATTR SR1MODE CE1_OVER_LSR1 LSR1_OVER_CE1 RSYNC1 CLK1 0 SEL1 0 CE1 1 LSR1 0 CIN 0 CLK0 0 SEL0 0 CE0 1 SR0MODEATTR SR0MODE CE0_OVER_LSR0 LSR0_OVER_CE0 ASYNC0 FSBMUX F5B K3_0 K3_1 K3_2 K3_3 K2_0 K2_1 K2_2 K2_3 K1_0 K1_1 K1_2 K1_3 K0_0 K0_1 K0_2 K0_3 F5A 0 LOGIC MLOGIC RIPPLE RAM ROM PFU MODES GSR ENABLED DISABLED 0 K3_0MUX A K3 B K3_2MUX C D K2_0MUX A K2 B K2_2MUX C D A K1 B C D A K0 B C D F5AMUX DIN0 0 DIN0MUX H1H0MUX LUT6MUX DIN2 0 DIN2MUX REG2 D0 D1 SD SP CK LSR H3H2MUX BMUX DIN3 0 DIN3MUX REG3 D0 D1 SD SP CK LSR Q3 RESET SET DEL0 DEL1 DEL2 DEL3 Q2 RESET SET DEL0 DEL1 DEL2 DEL3 LSR0 0 LSR0MUX 1 CE0MUX 1 SEL0MUX CEBMUX THIS IS ALWAYS A FLIPFLOP CLK0MUX CINMUX COUT LSR1MUX 0 LSR47MUX CE1MUX 1 CE47MUX SEL1MUX 0 K7_0MUX AMUX DIN7 A K7 B K7_2MUX C D K6_0MUX A K6 B K6_2MUX C D A K5 B C D A K4 B C D FSCMUX DIN4 0 CLK1MUX DIN4MUX H5H4MUX LUT6MUX DIN6 0 DIN6MUX REG6 D0 D1 SD SP CK LSR H7H6MUX 0 DIN7MUX REG7 D0 D1 SD SP CK LSR Q7 RESET SET DEL0 DEL1 DEL2 DEL3 Q6 RESET SET DEL0 DEL1 DEL2 DEL3
F7
F6
LUT647
F5
DIN5 0 DIN5MUX REG5 D0 D1 SD SP CK LSR REG4 D0 D1 SD SP CK LSR Q5 RESET SET DEL0 DEL1 DEL2 DEL3 Q4 RESET SET DEL0 DEL1 DEL2 DEL3
F4
REGMODE_TOP FF LATCH REG 4 THROUGH 7
0
CE03MUX REG8 D0 SP CK LSR RECCOUT RESET SET DEL0 DEL1 DEL2 DEL3
LSRBMUX
0
LSR03MUX
F3
F2
LUT603
F1
DIN1 0 DIN1MUX REG1 D0 D1 SD SP CK LSR REG0 D0 D1 SD SP CK LSR Q1 RESET SET DEL0 DEL1 DEL2 DEL3 Q0 RESET SET DEL0 DEL1 DEL2 DEL3
F0
REGMODE_BOT FF LATCH REG 0 THROUGH 3
5-9714(F)
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 3. Simplified PFU Diagram Lattice Semiconductor 9
ORCA Series 4 FPGAs
Data Sheet May, 2006
Programmable Logic Cells (continued)
Look-Up Table Operating Modes
The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For example, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode, the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT memory. Table 2 lists the basic operating modes of the LUT. Figure 4--Figure 7 show block diagrams of the LUT operating modes. The accompanying descriptions demonstrate each mode's use for generating logic. Table 2. Look-Up Table Operating Modes Mode Logic Function
4-, 5-, and 6-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct input to ninth FF or as pass through to COUT. Half Logic/ Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode; Half Ripple CIN and ninth FF for logic or ripple functions. Ripple All LUTs combined to perform ripple-through data functions. Eight LUT registers available for direct-in use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of ripple mode are adder/subtractor, counter, multiplier, and comparator. Memory All LUTs and latches/FFs used to create a 32x4 synchronous dual-port RAM. Can be used as single-port or as ROM. PFU Control Inputs Each PFU has eight routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that affects all latches and FFs in the device. The eight control inputs are CLK[1:0], LSR[1:0], CE[1:0], and SEL[1:0], and their functionality for each logic mode of the PFU is shown in Table 3. The clock signal to the PFU is CLK, CE stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be configured as synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a function of the signal itself. SEL is used to dynamically select between direct PFU input and LUT output data as the input to the latches/FFs. All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable indicates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs are routed to the latches/FFs. Table 3. Control Input Functionality Mode Logic CLK[1:0] CLK to all latches/ FFs LSR[1:0] LSR to all latches/FFs, enabled per nibble and for ninth FF LSR to all latches/FF, enabled per nibble and for ninth FF LSR to all latches/FFs, enabled per nibble and for ninth FF LSR0 Port enable 2 CE[1:0] CE to all latches/FFs, selectable per nibble and for ninth FF CE to all latches/FFs, selectable per nibble and for ninth FF CE to all latches/FFs, selectable per nibble and for ninth FF CE1 RAM write enable CE0 Port enable 1 Not used SEL[1:0] Select between LUT input and direct input for eight latches/FFs Select between LUT input and direct input for eight latches/FFs Select between LUT input and direct input for eight latches/FFs Not used Not used Lattice Semiconductor
Half Logic/ CLK to all latches/ Half Ripple FFs Ripple CLK to all latches/ FFs CLK to RAM
Memory (RAM) Memory (ROM) 10
Optional for Not used synchronous outputs
Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
Logic Mode The PFU diagram of Figure 3 represents the logic mode of operation. In logic mode, the eight LUTs are used individually or in flexible groups to implement user logic functions. The latches/FFs may be used in conjunction with the LUTs or separately with the direct PFU data inputs. There are three basic submodes of LUT operation in PFU logic mode: F4 mode, F5 mode, and the F6 mode. Combinations of the submodes are possible in each PFU. F4 mode, shown simplified in Figure 4, illustrates the uses of the basic 4-input LUTs in the PFU. The output of an F4 LUT can be passed out of the PFU, captured at the LUTs associated latch/FF, or multiplexed with the adjacent F4 LUT output using one of the F5[A:D] inputs to the PFU. Only adjacent LUT pairs (K0 and K1, K2 and K3, K4 and K5, K6 and K7) can be multiplexed, and the output always goes to the even-numbered output of the pair. The F5 submode of the LUT operation, shown simplified in Figure 4, indicates the use of 5-input LUTs to implement logic. 5-input LUTs are created from two 4-input LUTs and a multiplexer. The F5 LUT is the same as the multiplexing of two F4 LUTs described previously with the constraint that the inputs to the F4 LUTs be the same. The F5[A:D] input is then used as the fifth LUT input. The equations for the two F4 LUTs will differ by the assumed value for the F5[A:D] input, one F4 LUT assuming that the F5[A:D] input is zero, and the other assuming it is a one. The selection of the appropriate F4 LUT output in the F5 MUX by the F5[A:D] signal creates a 5-input LUT. Any combination of F4 and F5 LUTs is allowed per PFU using the eight 16-bit LUTs. Examples are eight F4 LUTs, four F5 LUTs, and a combination of four F4 plus two F5 LUTs. Two 6-input LUTs are created by shorting together the input of four 4-input LUTs (K0:3 and K4:7) which are multiplexed together. The F5 inputs of the adjacent F4 LUTs derive the fifth and sixth inputs of the F6 mode. The F6 outputs, LUT603 and LUT647, are dedicated to the F6 mode or can be used as the outputs of MUX8x1. MUX8x1 modes are created by programming adjacent 4-input LUTs to 2x1 MUXs and multiplexing down to create MUX8x1. Both F6 mode and MUX8x1 are available in the upper and lower PFU nibbles.
K7 F7 K7_0 K7_1 K7_2 K7_3 F5D K6_0 K6_1 K6_2 K6_3 2x1 MUX LUT4
LUT4
F6
K6
F6
K5
F5
K5_0 K5_1 K5_2 K5_3 F5C K4_0 K4_1 K4_2 K4_3
LUT4
K4
F4
LUT4
2x1 MUX
F4
K3
F3
K3_0 K3_1 K3_2 K3_3 F5B K2_0 K2_1 K2_2 K2_3
LUT4
K2
F2
LUT4
2x1 MUX
F2
K1
F1
K1_0 K1_1 K1_2 K1_3 F5A K0_0 K0_1 K0_2 K0_3
LUT4
K0
F0
LUT4
2x1 MUX
F0
5-9733(F)
Figure 4. Simplified F4 and F5 Logic Modes
Lattice Semiconductor
11
ORCA Series 4 FPGAs
Data Sheet May, 2006
Programmable Logic Cells (continued)
K7_0 K7_1 K7_2 K7_0 K7_1 K7_2 K7_3 F5D K6_0 K6_1 K6_2 K6_3 K5_0 K5_1 K5_2 K5_3 F5C K4_0 K4_1 K4_2 K4_3 LUT4 LUT4 K5_0 K5_1 K5_2 F5C K4_0 K4_1 K4_2 LUT4 2x1 MUX F3 F5D LUT4 K6_0 K6_1 K6_2 LUT4 2x1 MUX F4 LUT4
LUT4
4x1 MUX
LUT647
LUT4
K3_0 K3_1 K3_2 K3_3 F5B K2_0 K2_1 K2_2 K2_3 K1_0 K1_1 K1_2 K1_3 F5A K0_0 K0_1 K0_2 K0_3
K3_0 K3_1 K3_2 LUT4 F5B K2_0 K2_1 K2_2 LUT4
LUT4
LUT4
2x1 MUX
F2
LUT4
4x1 MUX
LUT603
K1_0 K1_1 K1_2 F5A
LUT4
LUT4
K0_0 K0_1 K0_2 5-9734(F)a
LUT4
2x1 MUX
F0
Figure 5. Simplified F6 Logic Modes Figure 6. MUX 4x1
5-9735(F)
12
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
K7_0 K7_1 K7_2 F5D K6_0 K6_1 K6_2
LUT4
LUT4
K5_0 K5_1 K5_2 F5C K4_0 K4_1 K4_2
4x1 MUX LUT4
MUX8x1 [LUT647]
LUT4
K3_0 K3_1 K3_2 F5B K2_0 K2_1 K2_2
LUT4
LUT4
K1_0 K1_1 K1_2 F5A K0_0 K0_1 K0_2
LUT4
4x1 MUX
MUX8x1 [LUT603]
LUT4
5-9736(F)a
Figure 7. MUX 8x1 Softwired LUT submode uses F4, F5 and F6 LUTs and internal PFU feedback routing to generate complex logic functions up to three LUT-levels deep. Multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs. In this manner, very complex logic functions, some of up to 22 inputs, can be implemented in a single PFU at greatly enhanced speeds. It is important to note that an LUT output that is fed back for softwired use is still available to be registered or output from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger equation need only be generated once, and PLC routing resources will not be required to use it in the larger equation.
Lattice Semiconductor
13
ORCA Series 4 FPGAs
Data Sheet May, 2006
Programmable Logic Cells (continued)
F4 F4 F4 F4 F5 F5
F4
F4
F4
F4
F5
F5
FOUR 7-INPUT FUNCTIONS IN ONE PFU
TWO 9-INPUT FUNCTIONS IN ONE PFU
F5
F4
F4
F4
F4
F5
F5
F5
F5
F5
ONE 17-INPUT FUNCTION IN ONE PFU
ONE 21-INPUT FUNCTION IN ONE PFU
5-5753(F)
F4
F4
F4
3
F4
F4
F4
F4
F4
TWO 10-INPUT FUNCTIONS IN ONE PFU
ONE OF TWO 21-INPUT FUNCTIONS IN ONE PFU
F4
F4
F4
F4
F5
F6
ONE 22-INPUT FUNCTION IN ONE PFU F4 4-INPUTLUT F5 5-INPUTLUT F6 6-INPUTLUT
5-5754(F)
Figure 8. Softwired LUT Topology Examples 14 Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
ripple operation (K7, F[7:0]) and half-logic ripple operation (K3, F[3:0]), respectively. The ripple mode diagram (Figure 9) shows full PFU ripple operation, with half-logic ripple connections shown as dashed lines. The result output and ripple output are calculated by using generate/propagate circuitry. In ripple mode, the two operands are input into KZ[1] and KZ[0] of each LUT. The result bits, one per LUT, are F[7:0]/F[3:0] (see Figure 9). The ripple output from LUT K7/K3 can be routed on dedicated carry circuitry into any of four adjacent PLCs, and it can be placed on the PFU COUT/ FCOUT outputs. This allows the PLCs to be cascaded in the ripple mode so that nibble-wide ripple functions can be expanded easily to any length. Result outputs and the carry-out may optionally be registered within the PFU. The capability to register the ripple results, including the carry output, provides for improved counter performance and simplified pipelining in arithmetic functions.
Programmable Logic Cells (continued)
Half-Logic Mode Series 4 FPGAs are based upon a twin-quad architecture in the PFUs. The byte-wide nature (eight LUTs, eight latches/FFs) may just as easily be viewed as two nibbles (two sets of four LUTs, four latches/FFs). The two nibbles of the PFU are organized so that any nibble-wide feature (excluding some softwired LUT topologies) can be swapped with any other nibble-wide feature in another PFU. This provides for very flexible use of logic and for extremely flexible routing. The halflogic mode of the PFU takes advantage of the twinquad architecture and allows half of a PFU, K[7:4] and associated latches/FFs, to be used in logic mode while the other half of the PFU, K[3:0] and associated latches/FFs, is used in ripple mode. In half-logic mode, the ninth FF may be used as a general-purpose FF or as a register in the ripple mode carry chain. Ripple Mode The PFU LUTs can be combined to do byte-wide ripple functions with high-speed carry logic. Each LUT has a dedicated carry-out net to route the carry to/from any adjacent LUT. Using the internal carry circuits, fast arithmetic, counter, and comparison functions can be implemented in one PFU. Similarly, each PFU has carry-in (CIN, FCIN) and carry-out (COUT, FCOUT) ports for fast-carry routing between adjacent PFUs. The ripple mode is generally used in operations on two data buses. A single PFU can support an 8-bit ripple function. Data buses of 4 bits and less can use the nibble-wide ripple chain that is available in half-logic mode. This nibble-wide ripple chain is also useful for longer ripple chains where the length modulo 8 is four or less. For example, a 12-bit adder (12 modulo 8 = 4) can be implemented in one PFU in ripple mode (8 bits) and one PFU in half-logic mode (4 bits), freeing half of a PFU for general logic mode functions. Each LUT has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. A single bit is rippled from the previous LUT and is used as input into the current LUT. For LUT K0, the ripple input is from the PFU CIN or FCIN port. The CIN/FCIN data can come from either the fast-carry routing (FCIN) or the PFU input (CIN), or it can be tied to logic 1 or logic 0. In the following discussions, the notations LUT K7/K3 and F[7:0]/F[3:0] are used to denote the LUT that provides the carry-out and the data outputs for full PFU
C
DQ
REGOUT FCOUT
C K7[1] K7[0] K6[1] K6[0] K5[1] K5[0] K4[1] K4[0] K3[1] K3[0] K2[1] K2[0] K1[1] K1[0] K0[1] K0[0] CIN/FCIN
COUT F7
K7
DQ
Q7 F6
K6
DQ
Q6 F5
K5
DQ
Q5 F4
K4
DQ
Q4 F3
K3
DQ
Q3 F2
K2
DQ
Q2 F1
K1
DQ
Q1 F0
K0
DQ
Q0
5-5755(F).
Figure 9. Ripple Mode
Lattice Semiconductor
15
ORCA Series 4 FPGAs
Data Sheet May, 2006
Programmable Logic Cells (continued)
The ripple mode can be used in one of four submodes. The first of these is adder-subtractor submode. In this submode, each LUT generates three separate outputs. One of the three outputs selects whether the carry-in is to be propagated to the carry-out of the current LUT or if the carry-out needs to be generated. If the carry-out needs to be generated, this is provided by the second LUT output. The result of this selection is placed on the carry-out signal, which is connected to the next LUT carry-in or the COUT/FCOUT signal, if it is the last LUT (K7/K3). Both of these outputs can be any equation created from KZ[1] and KZ[0], but in this case, they have been set to the propagate and generate functions. The third LUT output creates the result bit for each LUT output connected to F[7:0]/F[3:0]. If an adder/subtractor is needed, the control signal to select addition or subtraction is input on F5A/F5C inputs. These inputs generate the controller input AS. When AS = 0 this function performs the adder, A + B. When AS = 1 the function performs the subtractor, A - B. The result bit is created in one-half of the LUT from a single bit from each input bus KZ[1:0], along with the ripple input bit. The second submode is the counter submode (see Figure 10). The present count, which may be initialized via the PFU DIN inputs to the latches/FFs, is supplied to input KZ[0], and then output F[7:0]/F[3:0] will either be incremented by one for an up counter or decremented by one for a down counter. If an up/down counter is needed, the control signal to select the direction (up or down) is input on F5A and F5C. When F5[A:C], respectively per nibble, is a logic 1, this indicates a down counter and a logic 0 indicates an up counter.
C D Q REGCOUT FCOUT C K7[0] K7 K6[0] K6 K5[0] K5 K4[0] K4 K3[0] K3 K2[0] K2 K1[0] K1 K0[0] K0 CIN/FCIN
5-5756(F)
COUT F7 D Q Q7 F6 D Q Q6 F5 D Q Q5 F4 D Q Q4 F3 D Q Q3 F2 D Q Q2 F1 D Q Q1 F0 D Q Q0
Figure 10. Counter Submode
16
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
In the third submode, multiplier submode, a single PFU can affect an 8x1 bit (4x1 for half-ripple mode) multiply and sum with a partial product (see Figure 11). The multiplier bit is input at F5[A:C], respectively per nibble, and the multiplicand bits are input at KZ[1], where K7[1] is the most significant bit (MSB). KZ[0] contains the partial product (or other input to be summed) from a previous stage. If F5[A:C] is logical 1, the multiplicand is added to the partial product. If F5[A:C] is logical 0, 0 is added to the partial product, which is the same as passing the partial product. CIN/FCIN can bring the carry-in from the less significant PFUs if the multiplicand is wider than 8 bits, and COUT/FCOUT holds any carry-out from the multiplication, which may then be used as part of the product or routed to another PFU in multiplier mode for multiplicand width expansion. Ripple mode's fourth submode features equality comparators. The functions that are explicitly available are A B, A B, and A B, where the value for A is input on KZ[0], and the value for B is input on KZ[1]. A value of 1 on the carry-out signals valid argument. For example, a carry-out equal to 1 in AB submode indicates that the value on KZ[0] is greater than or equal to the value on KZ[1]. Conversely, the functions A B, A + B, and A > B are available using the same functions but with a 0 output expected. For example, A > B with a 0 output indicates A B. Table 4 shows each function and the output expected. If larger than 8 bits, the carry-out signal can be cascaded using fast-carry logic to the carry-in of any adjacent PFU. The use of this submode could be shown using Figure 9, except that the CIN/FCIN input for the least significant PFU is controlled via configuration. Table 4. Ripple Mode Equality Comparator Functions and Outputs Equality Function AB AB AB AB A=B ispLEVER Submode AB AB AB AB AB AB True, if Carry-Out Is: 1 1 1 0 0 0
C DQ REGCOUT
F5[A:C] K7[1] 0 K7[0] K6[1] 0 K6[0] K5[1] 0 K5[0] K4[1] 0 K4[0] K3[1] 0 K3[0] K2[1] 0 K2[0] K1[1] 0 K1[0] K0[1] 0 K0[0] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
C F7 + K7 F6 + K6 F5 + K5 F4 + K4 F3 + K3 F2 + K2 F1 + K1 F0 + K0 D Q Q0 D Q Q1 D Q Q2 D Q Q3 D Q Q4 D Q Q5 D Q Q6 D Q Q7
COUT
5-5757(F)
Key: C = configuration data. Note: F5[A:C] shorted together
Figure 11. Multiplier Submode
Lattice Semiconductor
17
ORCA Series 4 FPGAs
Data Sheet May, 2006
Programmable Logic Cells (continued)
Memory Mode The Series 4 PFU can be used to implement a 32x4 (128-bit) synchronous, dual-port RAM). A block diagram of a PFU in memory mode is shown in Figure 12. This RAM can also be configured to work as a single-port memory and because initial values can be loaded into the RAM during configuration, it can also be used as a ROM.
F5[A:D] KZ[3:0] CIN(WA1) DQ 4 5
READ ADDRESS[4:0] WRITE ADDRESS[4:0]
DIN7(WA3)
DQ F6 F4 F2 F0
DIN5(WA2)
DQ
DQ DIN3(WA1) DQ DQ
Q6
DIN1(WA0)
DQ
READ DATA[3:0]
4
Q4
DQ DIN6(WD3) DQ 4 WRITE DATA[3:0] DQ DIN4(WD2) DQ
Q2
Q0
DIN2(WD1)
DQ
DIN0(WD0)
DQ
CE0, LSR0 (SEE NOTE 2.) CE1
DQ S/E
WRITE ENABLE RAM CLOCK
CLK[0:1]
5-5969(F)a
1. CLK[0:1] are commonly connected in memory mode. 2. CE1 = write enable = wren; wren = 0 (no write enable); wren = 1 (write enabled). CE0 = write port enable 0; CE0 = 0, wren = 0; CE0 = 1, wren = CE1. LSR0 = write port enable 1; LSR0 = 0, wren = CE0; LSR0 = 1, wren = CE1.
Figure 12. Memory Mode 18 Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Wider memories can be created by operating two or more memory mode PFUs in parallel, all with the same address and control signals, but each with a different nibble of data. To increase memory word depth above 32, two or more PLCs can be used. Figure 12 shows a 128x8 dual-port RAM that is implemented in eight PLCs. This figure demonstrates data path width expansion by placing two memories in parallel to achieve an 8-bit data path. Depth expansion is applied to achieve 128 words deep using the 32-word deep PFU memories. In addition to the PFU in each PLC, the SLIC (described in the next section) in each PLC is used for read address decodes and 3-state drivers. The 128x8 RAM shown could be made to operate as a single-port RAM by tying (bit-for-bit) the read and write addresses. To achieve depth expansion, one or two of the write address bits (generally the MSBs) are routed to the write port enables as in Figure 12. For 2 bits, the bits select which 32-word bank of RAM of the four available from a decode of two WPE inputs is to be written. Similarly, 2 bits of the read address are decoded in the SLIC and are used to control the 3-state buffers through which the read data passes. The write data bus is common, with separate nibbles for width expansion, across all PLCs, and the read data bus is common (again, with separate nibbles) to all PLCs at the output of the 3-state buffers. Figure 13 also shows the capability to provide a read enable for RAMs/ROMs using the SLIC cell. The read enable will 3-state the read data bus when inactive, allowing the write data and read data buses to be tied together if desired.
Programmable Logic Cells (continued)
The PFU memory mode uses all LUTs and latches/FFs including the ninth FF in its implementation as shown in Figure 12. The read address is input at the KZ[3:0] and F5[A:D] inputs where KZ[0] is the LSB and F5[A:D] is the MSB, and the write address is input on CIN (MSB) and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write data is input on DIN[6, 4, 2, 0], where DIN[6] is the MSB, and read data is available combinatorially on F[6, 4, 2, 0] and registered on Q[6, 4, 2, 0] with F[6] and Q[6] being the MSB. The write enable controlling ports are input on CE0, CE1, and LSR0. CE1 is the activehigh write enable (CE1 = 1, RAM is write enabled). The first write port is enabled by CE0. The second write port is enabled with LSR0. The PFU CLK (CLK0) signal is used to synchronously write the data. The polarities of the clock, write enable, and port enables are all programmable. Write-port enables may be disabled if they are not to be used. Data is written to the write data, write address, and write enable registers on the active edge of the clock, but data is not written into the RAM until the next clock edge one-half cycle later. The read port is actually asynchronous, providing the user with read data very quickly after setting the read address, but timing is also provided so that the read port may be treated as fully synchronous for write then read applications. If the read and write address lines are tied together (maintaining MSB to MSB, etc.), then the dual-port RAM operates as a synchronous single-port RAM. If the write enable is disabled, and an initial memory contents is provided at configuration time, the memory acts as a ROM (the write data and write address ports and write port enables are not used).
Lattice Semiconductor
19
ORCA Series 4 FPGAs
Data Sheet May, 2006
Programmable Logic Cells (continued)
WD[7:0] 8 4 PLC 4 PLC 4 PLC 4 PLC
WD[7:4] 5 WA WPE 1 WPE 2 WE RD[7:4] RA 5 5
WD[3:0] WA WPE 1 WPE 2 WE RD[3:0] RA 5 5
WD[7:4] WA WPE 1 WPE 2 WE RD[7:4] RA 5 5
WD[3:0] WA WPE 1 WPE 2 WE RD[3:0] RA 5
RE 4 RD[7:0] WE WA[6:0] RA[6:0] CLK RE 7 7 8 4
RE 4
RE 4
RE
5-5749(F)
Figure 13. Memory Mode Expansion Example--128x8 RAM
Supplemental Logic and Interconnect Cell
Each PLC contains a SLIC embedded within the PLC routing, outside of the PFU. As its name indicates, the SLIC performs both logic and interconnect (routing) functions. Its main features are 3-statable, bidirectional buffers, and a PAL-like decoder capability. Figure 14 shows a diagram of a SLIC with all of its features shown. All modes of the SLIC are not available at one time. The ten SLIC inputs can be sourced directly from the PFU or from the general routing fabric. SI[0:9] inputs can come from the horizontal or vertical routing and I[0:9} comes from the PFU outputs O[9:0]. These inputs can also be tied to a logical 1 or 0 constant. The inputs are twin-quad in nature and are segregated into two groups of four nibbles and a third group of two inputs for control. Each input nibble groups also have 3-state capability, however the third pair does not. There is one 3-state control (TRI) for each SLIC, with the capability to invert or disable the 3-state control for each group of four BIDIs. Separate 3-state control for each nibble-wide group is achievable by using the SLICs decoder (DEC) output, driven by the group of two BIDIs, to control the 3-state of one BIDI nibble 20
while using the TRI signal to control the 3-state of the other BIDI nibble. Figure 15 shows the SLIC in buffer mode with available 3-state control from the TRI and DEC signals. If the entire SLIC is acting in a buffer capacity, the DEC output may be used to generate a constant logic 1 (VHI) or logic 0 (VLO) signal for general use. The SLIC may also be used to generate PAL-like ANDOR with optional INVERT (AOI) functions or a decoder of up to 10 bits. Each group of buffers can feed into an AND gate (4-input AND for the nibble groups and 2-input AND for the other two buffers). These AND gates then feed into a 3-input gate that can be configured as either an AND gate or an OR gate. The output of the 3-input gate is invertible and is output at the DEC output of the SLIC. Figure 19 shows the SLIC in full decoder mode. The functionality of the SLIC is parsed by the two nibble-wide groups and the 2-bit buffer group. Each of these groups may operate independently as BIDI buffers (with or without 3-state capability for the nibblewide groups) or as a PAL/decoder.
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
As discussed in the memory mode section, if the SLIC is placed into one of the modes where it contains both buffers and a decode or AOI function (e.g., BUF_BUF_DEC mode), the DEC output can be gated with the 3-state input signal. This allows up to a 6-input decode (e.g., BUF_DEC_DEC mode) plus the 3-state input to control the enable/disable of up to four buffers per SLIC Figure 15--Figure 19 show several configurations of the SLIC, while Table 5 shows all of the possible modes. Table 5. SLIC Modes Mode No. 1 2 3 4 5 6 7 8 Mode BUFFER BUF_BUF_DEC BUF_DEC_BUF BUF_DEC_DEC DEC_BUF_BUF DEC_BUF_DEC DEC_DEC_BUF DECODER BUF [3:0] Buffer Buffer Buffer Buffer Decoder Decoder Decoder Decoder BUF [7:4] Buffer Buffer Decoder Decoder Buffer Buffer Decoder Decoder BUF [9:8] Buffer Decoder Buffer Decoder Buffer Decoder Buffer Decoder
SIN9 I9 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SOUT08 SOUT09
SIN7 I7 LOGIC 1 OR 0 SIN6 I6 LOGIC 1 OR 0 SIN5 I5 LOGIC 1 OR 0 SIN4 I4 LOGIC 1 OR 0 TRI 0/1 DEC 0/1 0/1 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0 0/1
SOUT07
SOUT06
SOUT05 DEC SOUT04
SOUT03
SOUT02
SOUT01
SOUT00
5-5744(F).a.
Figure 14. SLIC All Modes Diagram
Lattice Semiconductor
21
ORCA Series 4 FPGAs
Data Sheet May, 2006
Programmable Logic Cells (continued)
SIN9 SIN9 I9 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SIN7 SIN7 I7 LOGIC 1 OR 0 SIN6 I6 LOGIC 1 OR 0 SIN5 I5 LOGIC 1 OR 0 SIN4 I4 LOGIC 1 OR 0 1 TRI 0/1 1 0 THIS CAN BE USED TO GENERATE A VHI OR VLO 0/1 SIN3 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0
5-5745(F).a
I9 SOUT09 LOGIC 1 OR 0 SIN8 I8 SOUT08 LOGIC 1 OR 0
I7 SOUT07 LOGIC 1 OR 0 SIN6 I6 SOUT06 LOGIC 1 OR 0 SIN5 I5 SOUT05 LOGIC 1 OR 0 SIN4 I4 SOUT04 LOGIC 1 OR 0
SOUT07
SOUT06
SOUT05
SOUT04
TRI 1 DEC 1
DEC
1 I3 SOUT03
SOUT03
LOGIC 1 OR 0 SIN2 I2 SOUT02
SOUT02
LOGIC 1 OR 0 SIN1 I1 SOUT01
SOUT01
LOGIC 1 OR 0 SIN0 I0 SOUT00
SOUT00
LOGIC 1 OR 0
5-5746(F).a
Figure 16. Buffer-Buffer-Decoder Mode
Figure 15. Buffer Mode
22
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
SIN9
SIN9 I9 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SIN7 SOUT08 SOUT09
LOGIC 1 OR 0 SIN8
LOGIC 1 OR 0
SIN7
LOGIC 1 OR 0 SIN6
LOGIC 1 OR 0 SIN6
LOGIC 1 OR 0 SIN5
LOGIC 1 OR 0 SIN5
LOGIC 1 OR 0 SIN4
LOGIC 1 OR 0 SIN4
LOGIC 1 OR 0 DEC TRI
LOGIC 1 OR 0
1
TRI
DEC
1 SIN3 I3 SOUT03 IF LOW THEN 3 STATE BUFFERS ARE HIGH Z
1
LOGIC 1 OR 0 SIN2
1 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0
5-5747(F).a
I2 LOGIC 1 OR 0
SOUT02
SOUT03
SIN1 I1 LOGIC 1 OR 0 SOUT01
SOUT02
SIN0 I0 LOGIC 1 OR 0
5-5750(F)
SOUT00
SOUT01
Figure 18. Buffer-Decoder-Decoder Mode
SOUT00
Figure 17. Buffer-Decoder-Buffer Mode
Lattice Semiconductor
23
ORCA Series 4 FPGAs
Data Sheet May, 2006
PLC Latches/Flip-Flops
The eight general-purpose latches/FFs in the PFU can be used in a variety of configurations. In some cases, the configuration options apply to all eight latches/FFs in the PFU and some apply to the latches/FFs on a nibble-wide basis where the ninth FF is considered independently. For other options, each latch/FF is independently programmable. In addition, the ninth FF can be used for a variety of functions. Table 6 summarizes these latch/FF options. The latches/FFs can be configured as either positive- or negative-level sensitive latches, or positive or negative edge-triggered FFs (the ninth register can only be a FF). All latches/FFs in a given PFU share the same clock, and the clock to these latches/FFs can be inverted. The input into each latch/FF is from either the corresponding LUT output (F[7:0]) or the direct data input (DIN[7:0]). The latch/FF input can also be tied to logic 1 or to logic 0, which is the default. Table 6. Configuration RAM Controlled Latch/ Flip-Flop Operation Function Options
Programmable Logic Cells (continued)
SIN9
LOGIC 1 OR 0 SIN8
LOGIC 1 OR 0
SIN7
LOGIC 1 OR 0 SIN6
LOGIC 1 OR 0 SIN5
LOGIC 1 OR 0 SIN4
LOGIC 1 OR 0 DEC
SIN3
LOGIC 1 OR 0 SIN2
LOGIC 1 OR 0 SIN1
LOGIC 1 OR 0 SIN0
LOGIC 1 OR 0
5-5748(F)
Common to All Latches/FFs in PFU LSR Operation Asynchronous or synchronous. Clock Polarity Noninverted or inverted. Front-end Select* Direct (DIN[7:0]) or from LUT (F[7:0]). LSR Priority Either LSR or CE has priority. Latch/FF Mode Latch or FF. Enable GSRN GSRN enabled or has no effect on PFU latches/FFs. Set Individually in Each Latch/FF in PFU Set/Reset Mode Set or reset. By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8]) Clock Enable CE or none. LSR Control LSR or none.
* Not available for FF[8].
Figure 19. Decoder Mode
Each PFU has two independent programmable clocks, clock enable CE[1:0], local set/reset LSR[1:0], and front end data selects SEL[1:0]. When CE is disabled, each latch/FF retains its previous value when clocked. The clock enable, LSR, and SEL inputs can be inverted to be active-low.
24
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
latch/FF is from the output of its associated LUT, F[7:0], or direct from DIN[7:0], bypassing the LUT. In the front-end data select mode, both signals are available to the latches/FFs. If either or both of these inputs is unused or is unavailable, the latch/FF data input can be tied to a logic 0 or logic 1 instead (the default is logic 0). The latches/FFs can be configured in three basic modes:
Programmable Logic Cells (continued)
The set/reset operation of the latch/FF is controlled by two parameters: reset mode and set/reset value. When the GSRN and local set/reset (LSR) signals are not asserted, the latch/FF operates normally. The reset mode is used to select a synchronous or asynchronous LSR operation. If synchronous, LSR has the option to be enabled only if clock enable (CE) is active or for LSR to have priority over the clock enable input, thereby setting/resetting the FF independent of the state of the clock enable. The clock enable is supported on FFs, not latches. It is implemented by using a 2-input multiplexer on the FF input, with one input being the previous state of the FF and the other input being the new data applied to the FF. The select of this 2-input multiplexer is clock enable (CE), which selects either the new data or the previous state. When the clock enable is inactive, the FF output does not change when the clock edge arrives. The GSRN signal is only asynchronous, and it sets/ resets all latches/FFs in the FPGA based upon the set/ reset configuration bit for each latch/FF. The set/reset value determines whether GSRN and LSR are set or reset inputs. The set/reset value is independent for each latch/FF. An option is available to disable the GSRN function per PFU after initial device configuration. The latch/FF can be configured to have a data frontend select. Two data inputs are possible in the front-end select mode, with the SEL signal used to select which data input is used. The data input into each
Local synchronous set/reset: the input into the PFU's LSR port is used to synchronously set or reset each latch/FF. Local asynchronous set/reset: the input into LSR asynchronously sets or resets each latch/FF. Latch/FF with front-end select, LSR either synchronous or asynchronous: the data select signal selects the input into the latches/FFs between the LUT output and direct data in.
For all three modes, each latch/FF can be independently programmed as either set or reset. Figure 20 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. The ninth PFU FF, which is generally associated with registering the carry-out signal in ripple mode functions, can be used as a general-purpose FF. It is only an FF and is not capable of being configured as a latch. Because the ninth FF is not associated with an LUT, there is no front-end data select. The data input to the ninth FF is limited to the CIN input, logic 1, logic 0, or the carry-out in ripple and half-logic modes.
CE F DIN LOGIC 1 LOGIC 0 LSR S_RESET CLK SET RESET GSRN CD CD GSRN LSR CE D S_SET Q F DIN LOGIC 1 LOGIC 0
CE CE D Q
F DIN LOGIC 1 LOGIC 0
SEL D DIN
CE CE Q
CLK SET RESET
GSRN LSR
CLK SET RESET
CD
5-9737(F).a
Key: C = configuration data.
Figure 20. Latch/FF Set/Reset Configurations
Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006

Embedded Block RAM (EBR)
The ORCA Series 4 devices compliment the distributed PFU RAM with large blocks of memory macrocells. The memory is available in 512 words by 18 bits/word blocks with 2 read and 2 write ports with two byte lane enables which operate with quad-port functionality. Additional logic has been incorporated for FIFO, multiplier, and CAM implementations. The RAM blocks are organized along the PLC rows and are added in proportion to the FPGA array sizes as shown in Table 7. The contents of the RAM blocks may be optionally initialized during FPGA configuration. Table 7. ORCA Series 4-- Available Embedded Block RAM
Device OR4E02 OR4E04 OR4E06 Number of Blocks 8 12 16 Number of EBR Bits 74K 111K 147K
One 256 x 36 RAM. One 1K x 9 RAM. Two independent 512 x 9 RAMs built in one EBR with separate read clocks, write clocks and enables. Two independent RAMS with arbitrary number of words whose sum is 512 words or less by 18 bits/ word or less.
The joining of RAM blocks is supported to create wider deeper memories. The adjacent routing interface provided by the CIBs allow the cascading of blocks together with minimal penalties due to routing delays. It is also possible to connect any or all of the EBR RAM blocks together through the embedded system bus, which is discussed in a later section of this data sheet. Arbitration logic is optionally programmed by the user to signal occurrences of data collisions as well as to block both ports from writing at the same time. The arbitration logic prioritizes PORT1. When utilizing the arbiter, the signal BUSY indicates data is being written to PORT1. This BUSY output signals PORT1 activity by driving a high output. If the arbiter is turned off both ports could be written at the same time and the data would be corrupt. In this scenario the BUSY signal will indicate a possible error. There is also a user option which dedicates PORT 1 to communications to the system bus. In this mode the user logic only has access to PORT0 and arbitration logic is enabled. The system bus utilizes the priority given to it by the arbiter therefore the system bus will always be able to write to the EBR.
Each highly flexible 512x18 (quad-port, two read/two write) RAM block can be programmed by the user to meet their particular function. Each of the EBR configurations use the physical signals as shown in Table 8. Quad-port addressing permits simultaneous read and write operations on all four ports. The EBR ports are written synchronously on the positive-edge of CKW. Synchronous read operations uses the positive-edge of CKR. Options are available to use synchronous read address registers and read output registers, or to bypass these registers and have the RAM read operate asynchronously. Detailed information about the EBR blocks is found in various application notes. ispLEVER provides SCUBA as a RAM generation tool for EBR RAMs. Many of the EBR sub-modes are supported and the initialization values can also be defined.
EBR Features
Quad Port RAM Modes (Two Read/Two Write)
One 512 x 18 RAM with optional built-in write arbitration. One 1024 x 18 RAM built on two blocks with built-in decode logic for simplified implementation.
Dual Port RAM Modes (One Read/One Write)
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
An 8 x 8 MULTIPLY mode is configurable to either a pipelined or combinatorial multiplier function of two 8bit numbers. Two 8-bit operands are multiplied to yield a 16-bit product. The input can be registered in pipeline mode. CAM Mode The CAM block is a binary content address memory that provides fast address searches by receiving data input and returning addresses that contain the data. Implemented in each EBR are two 16-word x 8-bit CAM function blocks. The CAM has three modes, single match, multiple match and clear, which are all achieved in one clock cycle. In single match mode, a 8-bit data input is internally decoded and reports a match when data is present in a particular RAM address. Its result is reported by a corresponding single address bit. In multiple match the same occurs with the exception of multiple address lines report the match. Clear mode is used to clear the CAM contents by erasing all locations one cycle per location. The EBR blocks in CAM mode may be cascaded to produce larger CAMs.
Embedded Block RAM (EBR) (continued)
FIFO Modes FIFOs can be configured to 256, 512, or 1K depths and 36, 18, or 9 widths respectively but also can be expanded using multiple blocks. FIFO works synchronously with the same read and write clock where the read port can be registered on the output or not registered. It can also be optionally configured asynchronously with different read and write clocks and the same read port register options. Integrated flags allow the user the ability to fully utilize the EBR for FIFO, without the need to dedicate an address for providing distinct full/empty status. There are four programmable flags provided for each FIFO: Empty, partially empty, full, and partially full FIFO status. The partially empty and partially full flags are programmable with the flexibility to program the flags to any value from the full or empty threshold. The programmed values can be set to a fixed value through the bitstream or a dynamic value can be controlled by input pins of the EBR FIFO. When the FIFO is in asynchronous mode, the FIFO flags use grey code counters to ensure proper glitch-free operation. Multiplier Modes The ORCA Series 4 EBR supports two variations of multiplier functions. Constant coefficient MULTIPLY [KCM] mode will produce a 24-bit output of a fixed 8-bit constant multiply of a 16-bit number or a fixed 16-bit constant multiply of an 8-bit number. This KCM multiplies a constant times a 16- or 8-bit number and produces a product as a 24-bit result. The coefficient and multiplication tables are stored in memory. The input can be configured to be registered for pipelining. Both write ports are available during MULTIPLY mode so that the user logic can update and modify the coefficients for dynamic coefficient updates. The SCUBA program in ispLEVER should be used to create the KCM multipliers, including the input of initial coefficients.
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ORCA Series 4 FPGAs
Data Sheet May, 2006
Embedded Block RAM (EBR) (continued)
Table 8. RAM Signals
Port Signals I/O Function
PORT 0 AR0[#:0] AW0[#:0] BW0<1:0>
I I I
CKR0 CKW0 CSR0 CSW0 D [#:0] Q [#:0] PORT 1 AR1[#:0] AW1[#:0] BW1<1:0>
I I I I I O
Address to be read (variable width depending on RAM size). Address to be written (variable width depending on RAM size). Byte-write enable. Byte = 8-bits + parity bit. <1> = bits[17, 15:9] <0> = bits[16, 7:0] Positive-edge asynchronous read clock. Positive-edge synchronous write clock. Enables read to output. Active high. Enables write to output. Active high. Input data to be written to RAM (variable width depending on RAM size). Output data of memory contents at referenced address (variable width depending on RAM size). Address to be read (variable width depending on RAM size). Address to be written (variable width depending on RAM size). Byte-write enable. Byte = 8-bits + parity bit. <1> = bits[17, 15:9] <0> = bits[16, 7:0] Positive-edge asynchronous read clock. Positive-edge synchronous write clock. Enables read to output. Active high. Enables write to output. Active high. Input data to be written to RAM (variable width depending on RAM size). Output data of memory contents at referenced address (variable width depending on RAM size). PORT1 writing. Active high. Data output registers cleared. Memory contents unaffected. Active-low.
I I I
CKR1 CKW1 CSR1 CSW1 D [#:0] Q [#:0] Control BUSY RESET
I I I I I O
O I
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Embedded Block RAM (continued)
CKWPL CKW CSWSU CSW AWSU AW DSU D BWSU BW d BWH c DH AWH CSWH CKWPH
AR
a AQH
b
c AQ b c CKWQ d
0308(F)
Q
a
Figure 21. EBR Read and Write Cycles with Write Through and Nonregistered Read Port Table 9. FIFO Signals Port Signals AR0[5:0] AR1[9:0] FF PFF PEF EF D0[17:0] D1[17:0] CKW[0:1] CKR[0:1] CSW[1:0] CSR[1:0] RESET Q0[17:0] Q1[17:0] I/O I I O O O O I I I I I I I O O Function Programs FIFO flags. Used for partially empty flag size. Programs FIFO flags. Used for partially full flag size. Full Flag. Partially Full Flag. Partially Empty Flag. Empty Flag. Data inputs for all configurations. Data inputs for 256x36 configurations only. Positive-edge write port clock. Port 1 only used for 256x36 configurations. Positive-edge read port clock. Port 1 only used for 256x36 configurations. Active-high write enable. Port 1 only used for 256x36 configurations. Active-high read enable. Port 1 only used for 256x36 configurations. Active-low Resets FIFO pointers. Data outputs for all configurations. Data outputs for 256x36 configurations.
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ORCA Series 4 FPGAs
Data Sheet May, 2006
Embedded Block RAM (continued)
Table 10. Constant Multiplier Signals Port Signals AR0[15:0] AW(1:0)[8:0] D(1:0)[17:0] CKW[0:1] CKR[0:1] CSW[1:0] CSR[1:0] Q[23:0] I/O I I I I I I I O Function Data input-operand. Address bits. Data inputs to load memory or change coefficient. Positive-edge write port clock. Positive-edge read port clock. Used for synchronous multiply mode. Active-high write enable. Active-high read enable. Data outputs-product result.
Table 11. 8x8 Multiplier Signals Port Signals AR0[7:0] AR1[7:0] CKR[0:1] CSR[1:0] Q[15:0] Table 12. CAM Signals Port Signals AR(1:0)[7:0] AW(1:0)[8:0] D(1:0)[17] D(1:0)[16] D(1:0)[3:0] CSW[1:0] CSR[1:0] Q(1:0)15:0] I/O I I I I I I I O Function Data Match. Data Write. Clear data active high. Single match active high. CAM address for data write. Active-high write enable. Enable for CAM data write. Active-high read enable. Enable for CAM data match. Decoded Data outputs. "1" corresponds to a data match at that address location. I/O I I I I O Function Data input-Multiplicand. Data input-Multiplier. Positive-edge read port clock. Used for synchronous multiply mode. Active-high read enable. Data outputs-product.
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Global Primary Clock Nets
The Series 4 FPGAs provide eight fully distributed global primary clock net routing resources. The scheme dedicates four of the eight resources to provide fast primary nets and four are available for general primary nets. The fast primary nets are targeted toward lowskew and small injection times while the general primary nets are also targeted toward low-skew but have more source connection flexibility. Fast access to the global primary nets can be sourced from two pairs of pads located in the center of each side of the device, from the programmable PLLs and dedicated network PLLs located in the corners, or from general routing at the center of the device or at the middle of any side of the device. The I/O pads are semi-dedicated in pairs for use of differential I/O clocking or single-ended I/O clock sources. However if these pads are not needed to source the clock network they can be utilized for general I/O. The clock routing scheme is patterned using vertical and horizontal routes which provide connectivity to all PLC columns.
Routing Resources
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. x1 routes cross width of one PLC and provide local connectivity to PFU and SLIC inputs and outputs. x6 lines cross width of 6 PLCs and are unidirectional and buffered with taps in the middle and on the end. Segments allow connectivity to PFU/SLIC outputs (driven at one end-point), other x6 lines (at end-points), and x1 lines for access to PFU/SLIC inputs. xH lines run vertically and horizontally the distance of half the device and are useful for driving medium/long distance 3-state routing. The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility translates into an improved capability to route designs at the required speeds even when the I/O signals have been locked to specific pins. The buffered routing capability also allows a very large fanout to be driven from each logic output, thus greatly reducing the amount of logic replication required by synthetic tools. Generally, the ispLEVER Development System is used to automatically route interconnections. Interactive routing with the ispLEVER design editor (EPIC) is also available for design optimization. The routing resources consist of switching circuitry and metal interconnect segments. Generally, the metal lines which carry the signals are designated as routing segments. The switching circuitry connects the routing segments, providing one or more of three basic functions: signal switching, amplification, and isolation. A net running from a PFU, EBR, or PIO output (source) to a PLC, EBR, or PIO input (destination) consists of one or more routing segments, connected by switching circuitry called configurable interconnect points (CIPs).
Secondary Clock and Control Nets
Secondary clock control and routing provides flexible clocking and control signalling for local regions. Since secondary nets usually have high fanouts and require low skew, the Series 4 devices utilize a spine and branch that uses x6 segments with high-speed connections provided from the spines to the branches. The branches then have high-speed connections to PLC, PIO, and EBR clock and control signals. This strategy provides a flexible connectivity and routes can be sourced from any I/O pin, all PLLs, or from PLC or EBR logic.
Secondary Edge Clock Nets and Fast Edge Clock Nets
Six secondary edge clock nets per side are distributed around the edges of the device and are available for every PIO. All PIOs and PLLs can drive the secondary edge clocks and are used in conjunction with the secondary spines discussed above to drive the same edge clock signal into the internal logic array. The edge secondary clocks provide fast injection to the PLC array and I/O registers. One of the six secondary edge clocks provided per side of the device is a special fast edge clock net that only clocks input registers for further reduced setup/hold times.This timing path can only be driven from one of the four PIO input pins in each PIC. 31
Clock Distribution Network
Clock distribution is made up of three types of clock networks: primary, secondary, and edge clocks. these are described below and more information is available in the Series 4 Clocking Strategies application note.
Lattice Semiconductor
ORCA Series 4 FPGAs
Data Sheet May, 2006
ated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-state signal can be registered or nonregistered. The Series 4 I/O logic has been enhanced to include modes for high-speed uplink and downlink capabilities. These modes are supported through shift register logic which divides down incoming data or multiplies up outgoing data. This new logic block also supports highspeed DDR mode requirements where data is clocked into and out of the I/O buffers on both edges of the clock. The new programmable I/O cell allows designers to select I/Os which meet many new communication standards permitting the device to hook up directly without any external interface translation. They support traditional FPGA standards as well as high-speed singleended and differential pair signaling (as shown in Table 13). Based on a programmable, bank-oriented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V I/O levels. The I/O on the OR4Exx Series devices allows compliance with PCI local bus (Rev. 2.2) 3.3 V signaling environments. The signaling environment used for each input buffer can be selected on a per-pin basis. The selection provides the appropriate I/O clamping diodes for PCI compliance. More information on the Series 4 programmable I/O structure is available in the various application notes.
Routing Resources (continued)
Cycle Stealing
A new feature in Series 4 FPGAs is the ability to steal time from one register-to-register path and use that time in either the previous path before the first register or in a later path after the last register. This is done through selectable clock delays for every PLC register, EBR register, and PIO register. There are four programmable delay settings, including the default zero added delay value. This allows performance increases on typical critical paths from 15% to 40%. ispLEVER includes software to automatically take advantage of this capability to increase overall system speed. This is done after place and route is completed and uses timing driven algorithms based on the customer's preference file. A hold time check is also performed to verify no minimum hold time issues are introduced. More information on this clocking feature, including how it can be used to improve device setup times, hold times, clock-to-out delays and can reduce ground bounce caused by switching outputs can be found in the Cycle Stealing application note.
Programmable Input/Output Cells (PIC)
Programmable I/O
The Series 4 programmable I/O addresses the demand for the flexibility to select I/O that meets system interface requirements. I/Os can be programmed in the same manner as in previous ORCA devices with the addition of new features which allow the user the flexibility to select new I/O types that support high-speed interfaces. Each PIC contains up to four programmable I/O (PIO) pads and are interfaced through a common interface block (CIB) to the FPGA array. The PIC is split into two pairs of I/O pads with each pair having independent clocks, clock enables, local set/reset, and global set/reset enable/disable. On the input side, each PIO contains a programmable latch/FF which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer with a PFU. On the output side of each PIO, an output from the PLC array can be routed to each output FF, and logic can be associated with each I/O pad. The output logic associ32
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Input/Output Cells (continued)
Table 13. Series 4 Programmable I/O Standards Standard LVTTL LVCMOS2 LVCMOS18 PCI LVDS Bused-LVDS LVPECL PECL GTL GTL+ HSTL-class I HTSL-class III and IV STTL3-class I and II SSTL2-class I and II VDDIO (V) 3.3 2.5 1.8 3.3 2.5 2.5 3.3 3.3 3.3 3.3 1.5 1.5 3.3 2.5 VREF (V) NA NA NA NA NA NA NA 2.0 0.8 1.0 0.75 0.9 1.5 1.25 General purpose. Interface Usage
PCI. Point to point and multi-drop backplanes, high noise immunity. Network backplanes, high noise immunity, bus architecture backplanes. Network backplanes, differential 100 MHz+ clocking, optical transceiver, high-speed networking. Backplanes. Backplane or processor interface. High-speed SRAM and networking interfaces. Synchronous DRAM interface.
Note: interfaces to DDR and ZBT memories are supported through the interface standards shown above.
The PIOs are located along the perimeter of the device. The PIO name is represented by a two-letter designation to indicate the side of the device on which it is located followed by a number to indicate the row or column in which it is located. The first letter, P, designates that the cell is a PIO and not a PLC. The second letter indicates the side of the array where the PIO is located. The four sides are left (L), right (R), top (T), and bottom (B). A number follows to indicate the PIC row or column. The individual I/O pad is indicated by a single letter (either A, B, C, or D) placed at the end of the PIO name. As an example, PL10A indicates a pad located on the left side of the array in the tenth row. Each PIC interfaces to four bond pads through four PIOs and contains the necessary routing resources to provide an interface between I/O pads and the CIBs. Each PIC contains input buffers, output buffers, routing resources, latches/FFs, and logic and can be configured as an input, output, or bidirectional I/O. Any PIO is capable of supporting the I/O standards listed in Table 13. The CIBs that connect to the PICs have significant local routing resources, similar to routing in the PLCs. This new routing increases the ability to fix user pinouts prior to placement and routing of a design and still maintain routability. The flexibility provided by the routing also provides for increased signal speed due to a greater variety of optimal signal paths. Included in the routing interface is a fast path from the input pins to the PFU logic. This feature allows for input signals to be very quickly processed by the SLIC decoder function and used on-chip or sent back off of the FPGA. A diagram of a single PIO is shown in Figure 22, and Table 14 provides an overview of the programmable functions in an I/O cell.
Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
Programmable Input/Output Cells (continued)
LVDS RESISTOR LEVELMODE OUTPUT SIDE LVTTL LVCMOS2 OUTSH OUTDD CLK AND NAND OR NOR XOR XNOR OUTDDMUX OUTDD 0 OUTFFMUX OUTFF 0 EC SC CE CEMUX0 CLK4MUX DEL0 DEL1 DEL2 DEL3 OUTSH PMUX OUTMUX OUTSHMUX CLK OUTDD TSMUX OUTREG OUTREG DO CK SP LSR 1 LSR LSRMUX 0 GSR ENABLED DISABLED CE_OVER_LSR LSR_OVER_CE ASYNC 5-9732(F) RESET SET LATCH FF P2MUX OUTDD USRTS TSREG 1 DO CK LSR RESET SET 0 IOPAD CE PULLMODE UP DOWN NONE NA 1 CEMUXI DEL0 DEL1 DEL2 DEL3 LATCHFF LATCH FF EC SC NORMAL INVERTED PLOGIC BUFMODE SLEW FAST NA LVCMOS18 PCI SSTL2 SSTL3 HSTL1 HSTL3 GTL GTLPLUS PECL LVPECL LVDS DELAY CELL INMUX D0 CK D1 CK SP LSR RESET SET INDDMUX INDD LATCHFF D0 INFF MILLIAMPS SIX TWELVE TWENTYFOUR NA KEEPERMODE OFF ON FAST INPUT INCK INPUT SIDE OFF ON
SRMODE
Figure 22. Series 4 PIO Image from ispLEVER Design Software
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
FF which is clocked by a global primary system clock. The combination of input register capability with nonregistered inputs provides for input signal demultiplexing without any additional resources. The PIO input signal is sent to both the input register and directly to the unregistered input (INDD). The signal is latched and output to routing at INFF. These signals may then be registered or otherwise processed in the PLCs. Every PIO input can also perform input double data rate (DDR) functions with no PLC resources required. This type of scheme is necessary for DDR applications which require data to be clocked in from the I/O on both edges of the clock. In this scheme the input of INFF and INSH are captured on the positive and negative edges of the clock. Table 14. PIO Options
Input InputSpeed FloatValue RegisterMode ClockSense KeeperMode LVDSResistor Output OutputSpeed OutputDrive Current OutputFunction OutputSense 3-StateSense ClockSense Logic Options I/OControls ClockEnable Set/ResetLevel Set/ResetType Set/ResetPriority GSRControl Option Fast,Delayed,Normal Pull-up,Pull-down,None Latch,FF,FastZeroHoldFF, None(directinput) Inverted,Noninverted on,off on,off Option Fast,Slew 12mA/6mA,6mA/3mA,or 24mA/12mA Normal,FastOpenDrain Active-high,Active-low Active-high,Active-low Inverted,Noninverted See Table 15 Option Active-high,Active-low, AlwaysEnabled Active-high,Active-low, NoLocalReset Synchronous,Asynchronous CEoverLSR,LSRoverCE EnableGSR,DisableGSR
Programmable Input/Output Cells
(continued)
Inputs
There are many major options on the PIO inputs that can be selected in the ispLEVER tools listed in Table 14. Inputs may have a pull-up or pull-down resistor selected on an input for signal stabilization and power management. Input signals in a PIO are passed to CIB routing and/or a fast route into the clock routing system. A fast input from one PIO per PIC is also available to drive the edge clock network for fast I/O timing to other nearby PIOs. There is also a programmable delay available on the input. When enabled, this delay affects the INFF and INDD signals of each PIO, but not the clock input. The delay allows any signal to have a guaranteed zero hold time when input. Inputs should have transition times of less than 100 ns and should not be left floating. For full swing inputs, the timing characterization is done for rise/fall times of 1 V/ns. If any pin is not used, it is 3-stated with an internal pull-up resistor enabled automatically after configuration. Floating inputs increase power consumption, produce oscillations, and increase system noise. The inputs in LVTTL, LVCMOS2, and LVCMOS18 modes have a typical hysteresis of approximately 250 mV to reduce sensitivity to input noise. The PIC contains input circuitry which provides protection against latch-up and electrostatic discharge. The other features of the PIO inputs relate to the latch/ FF structure in the input path. In latch mode, the input signal is fed to a latch that is clocked by either the primary, secondary, or edge clock signal. The clock may be inverted or noninverted. There is also a local set/ reset signal to the latch. The senses of these signals are also programmable as well as the capability to enable or disable the global set/reset signal and select the set/reset priority. The same control signals may also be used to control the input latch/FF when it is configured as a FF instead of a latch, with the addition of another control signal used as a clock enable. The PIOs are paired together and have independent CE, Set/reset, and GSRN control signals per PIO pair. There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a global primary system clock. The fast zero-hold mode of the PIO input takes advantage of a latch/FF combination to latch the data quickly for zero-hold using a fast edge clock before passing the data to the Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
Table 15. PIOLogicOptions Option AND NAND OR NOR XOR XNOR Description OutputlogicalANDofsignalsonOUTDD andclock. OutputlogicalNANDofsignalsonOUTDD andclock. OutputlogicalORofsignalsonOUTDD andclock. OutputlogicalNORofsignalsonOUTDD andclock. OutputlogicalXORofsignalsonOUTDD andclock. OutputlogicalXNORofsignalsonOUTDD andclock.
Programmable Input/Output Cells
(continued)
Outputs
The PIO's output drivers have programmable drive capability and slew rates. Two propagation delays (fast, slewlim) are available on output drivers. There are three combinations of programmable drive currents (24 mA sink/12 mA source, 12 mA sink/6 mA source, and 6 mA sink/3 mA source). At powerup, the output drivers are in slewlim mode with 12mA sink/6 mA source. If an output is not to be driven in the selected configuration mode, it is 3-stated with a pullup resistor. The output buffer signal can be inverted, and the 3-state control signal can be made active-high, activelow, or always enabled. In addition, this 3-state signal can be registered or nonregistered. Additionally, there is a fast, open-drain output option that directly connects the output signal to the 3-state control, allowing the output buffer to either drive to a logic 0 or 3-state, but never to drive to a logic 1. Every PIO output can perform output data multiplexing with no PLC resources required. This type of scheme is necessary for DDR applications which require data clocking out of the I/O on both edges of the clock. In this scheme the OUTFF and OUTSH are registered and sent out on both the positive and negative edges of the clock using an output multiplexor. This multiplexor is controlled by either the edge clock or system clock. This multiplexor can also be configured to select between one registered output from OUTFF and one nonregistered output from OUTDD. The PIC logic block can also generate logic functions based on the signals on the OUTDD and CLK ports of the PIO. The functions are AND, NAND, OR, NOR, XOR, and XNOR. Table 15 is provided as a summary of the PIO logic options.
PIO Register Control Signals The PIO latches/FFs have various clock, clock enable (CE), local set/reset (LSR), and GSRN controls. Table 16 provides a summary of these control signals and their effect on the PIO latches/FFs. Note that all control signals are optionally invertible. Table 16. PIO Register Control Signals Control Signal Effect/Functionality
EdgeClock Clocksinputfast-capturelatch;option(ECLK) allyclocksoutputFF,or 3-stateFF,orPIOshiftregisters. System Clocksinputlatch/FF;optionallyclocks Clock outputFF,or3-stateFF,orPIOshift (SCLK) registers. Clock Optionallyenables/disablesinputFF Enable(CE) (notavailableforinputlatchmode); optionallyenables/disablesoutputFF; separateCEinversioncapabilityfor inputandoutput. LocalSet/ Optiontodisable;affectsinputlatch/FF, Reset(LSR) outputFF,and3-stateFFifenabled. GlobalSet/ OptiontoenableordisableperPIO Reset afterinitialconfiguration. (GSRN) Set/Reset Theinputlatch/FF,outputFF,and3Mode stateFFareindividuallysetorresetby boththeLSRandGSRNinputs.
36
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
I/O Banks and Groups
Flexible I/O features allow the user to select the type of I/O needed to meet different high-speed interface requirements and these I/Os require different input references or supply voltages. The perimeter of the device is divided into eight banks of PIO buffers, as shown in Figure 23, and for each bank there is a separate VDDIO that supplies the correct input and output voltage for a particular standard. The user must supply the appropriate power supply to the VDDIO pin. Within a bank, several I/O standards may be mixed as long as they use a common VDDIO. The shaded section of the I/O banks in Figure 23 (banks 2, 3, and 4) are removed for FPSCs, to allow the embedded block to be placed on the side of the FPGA array. Bank 1 and bank 5 are also extended to the corners in FPSCs to incorporate more FPGA I/Os. Some interface standards require a specified threshold voltage known as VREF. To accommodate various VREF requirements, each bank is further divided into groups. In these modes, where a particular VREF is required, the device is automatically programmed to dedicate a VREF pin for each group of PIOs within a bank. The appropriate VREF voltage must be supplied by the user and connected to the VREF pin for each group. The VREF is dedicated exclusively to the group and cannot be intermixed within the group with other signaling requiring other VREF voltages. However, pins not requiring VREF can be mixed in the same group. When used to supply a reference voltage the VREF pad is no longer available to the user for general use. The VREF inputs should be well isolated to keep the reference voltage at a consistent level. Table17. Compatible Mixed I/O Standards VDDIOBank Voltage 3.3V 2.5V 1.8V 1.5V CompatibleStandards LVTTL,SSTL3-I,SSTL3-II,GTL+, GTL,LVPECL,PECL LVCMOS2,SSTL2-I,SSTL2-II,LVDS LVCMOS18 HSTLI,HSTLIII,HSTLIV
BANK 0 (TL)
BANK 1 (TC)
BANK 2 (TR)
BANK 7 (CL)
PLC ARRAY
BANK 6 (BL)
BANK 5 (BC)
BANK 4 (BR)
BANK 3 (CR)
0205(F).
Figure 23. ORCA High-Speed I/O Banks Differential I/O (LVDS and LVPECL) Series 4 devices support differential input, output, and input/output capabilities through pairs of PIOs. The two standards supported are LVDS and LVPECL. The LVDS differential pair I/O standard allows for highspeed, low-voltage swing and low-power interfaces defined by industry standards: ANSI/TIA/EIA-644 and IEEE 1596.3 SSI-LVDS. The general purpose standard is supplied without the need for an input reference supply and uses a low switching voltage which translates to low ac power dissipation. The ORCA LVDS I/O provides an integrated 100 termination resistor used to provide a differential voltage across the inputs of the receiver. The on-chip integration provides termination of the LVDS receiver without the need of discrete external board resistors. The user has the programmable option to enable termination per receiver pair for point-to-point applications or in multipoint interfaces limit the use of termination to bussed pairs. If the user chooses to terminate any differential receiver, a single LVDS_R pin is dedicated to connect a single 100 ( 1%) resistor to VSS which then enables an internal resistor matching circuit to provide a balance 100 ( 10%) termination across all process, voltage, and temperature. Experiments have also shown that enabling this 100 matching resistor for LVDS outputs also improves performance.
Lattice Semiconductor
37
ORCA Series 4 FPGAs
Data Sheet May, 2006
Bus Hold Each PIO can be programmed with a KEEPERMODE feature. This element is user programmed for bus hold requirements. This mode retains the last known state of a bus when the bus goes into 3-state. It prevents floating busses and saves system power. PIO Downlink/Uplink (Shift Registers) Each group of four PIOs in a PIC have access to an input/output shift register as shown in Figure 24. This feature allows high-speed input data to be divided down by 1/2 or 1/4 and output data can be multiplied by 2x or 4x its internal speed. Both the input and output shift registers can be programmed to operate at the same time and are controlled by the same clock and control signals. For input shift mode, the data from INDD from the PIO is connected to the input shift register. The input data is divided down and is driven to the routing through the INSH nodes. For output shift mode, the data from the OUTSH nodes are driven from the internal routing and connects to the output shift register. This output data is multiplied up and driven to the OUTDD signal on the PIOs. In 2x output mode or input mode, two of the four I/Os in a PIC can use the shift registers. While in 4x mode, only one I/O can use the shift registers. This also means that all differential I/Os on a Series 4 device can use 2x shift register mode, but 4x mode is only available for half of the differential I/Os. In 4x input mode, all the INSH nodes are used, while 2x mode uses INSH4 and INSH3 for one shift register and INSH2 and INSH1 for the second shift register. Similarly, the output shift register in 4x mode uses all the OUTSH signals. OUTSH2 and OUTSH1 are used for 2x output mode for one shift register and OUTSH4 and OUTSH3 are used for the other output shift register.
Programmable Input/Output Cells
(continued) High-Speed Memory Interfaces PIO features allow high-speed interfaces to external SRAM and/or DRAM devices. Series 4 I/O meet 200 MHz ZBT requirements when switching between write and read cycles. ZBT allows 100% use of bus cycles during back-to-back read/write and write/read cycles. However this maximum utilization of the bus increases probability of bus contention when the interfaced devices attempt to drive the bus to opposite logic values. The LVTTL I/O interfaces directly with commercial ZBT SRAMs signalling and allows the versatility to program the FPGA drive strengths from 6 mA to 24 mA. DDR allows data to be read on both the rising and the falling edge of the clock which delivers twice the bandwidth. DDR doubles the memory speed from SDRAMs or SRAMs without the need to increase clock frequency. The flexibility of the PIO allows at least 156 MHz/312 Mbits per second performance using the SSTL I/O or HSTL I/O features of the Series 4 devices. High-Speed Networking Interfaces Series 4 devices support many I/O standards used in networking. Two examples of this are the XGMII standard for 10 GbE (HSTL or SSTL I/Os) and the SPI-4 standard for various 10 Gbits/s network interfaces (LVDS I/Os). Both operate as a point-to-point link between devices that are forward clocked and transmit data on both clock edges (DDR). The XGMII interface is 36-bits wide per data flow direction and the SPI-4 interface is a 16-bit interface. The XGMII specification is 156 MHz/312 Mbits/s and the SPI-4 specification that can be met is 325 MHz/650 Mbits/s. More information about using ORCA for these applications can be found in the associated application note.
38
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
PIO
PIO
PIO
PIO
OUTDD
OUTDD
OUTDD
OUTDD SHIFT REGISTER INTO FPGA
OUTSH
OUTSH
OUTSH
OUTSH
INDD
INDD
INDD
INDD
SHIFT REGISTER OUT FROM FPGA CLK OUTSH4 OUTSH3 OUTSH2 OUTSH1
INTSH2
INSH4
INSH3
INSH1
0204(F).
Figure 24. PIO Shift Register
Special Function Blocks
Special function blocks in the Series 4 provide extra capabilities beyond general FPGA operation. These blocks reside in the corners and MIDs (middle interquad areas) of the FPGA array. Internal Oscillator The internal oscillator resides in the upper left corner of the FPGA array. It has output clock frequencies of 1.25 MHz and 10 MHz. The internal oscillator is the source of the internal CCLK used for configuration. It may also be used after configuration as a generalpurpose clock signal. Global Set/Reset (GSRN) The GSRN logic resides in the upper-left corner of the FPGA. GSRN is an invertible, default, active-low signal that is used to reset all of the user-accessible latches/ FFs on the device. GSRN is automatically asserted at powerup and during configuration of the device. Lattice Semiconductor
The timing of the release of GSRN at the end of configuration can be programmed in the start-up logic described below. Following configuration, GSRN may be connected to the RESET pin via dedicated routing, or it may be connected to any signal via normal routing. GSRN can also be controlled via a system bus register command. Within each PFU and PIO, individual FFs and latches can be programmed to either be set or reset when GSRN is asserted. Series 4 allows individual PFUs and PIOs to turn off the GSRN signal to its latches/FFs after configuration. The RESET input pad has a special relationship to GSRN. During configuration, the RESET input pad always initiates a configuration abort, as described in the FPGA States of Operation section. After configuration, the GSRN can either be disabled (the default), directly connected to the RESET input pad, or sourced by a lower-right corner signal. If the RESET input pad is not used as a global reset after configuration, this pad can be used as a normal input pad.
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ORCA Series 4 FPGAs
Data Sheet May, 2006
test data is transmitted serially into TDI of the first BSCAN device (U1), through TDO/TDI connections between BSCAN devices (U2 and U3), and out TDO of the last BSCAN device (U4). In this configuration, the TMS and TCK signals are routed to all boundary-scan ICs in parallel so that all boundary-scan components operate in the same state. In other configurations, multiple scan paths are used instead of a single ring. When multiple scan paths are used, each ring is independently controlled by its own TMS and TCK signals. Figure 26 provides a system interface for components used in the boundary-scan testing of PCBs. The three major components shown are the test host, boundaryscan support circuit, and the devices under test (DUTs). The DUTs shown here are ORCA Series FPGAs with dedicated boundary-scan circuitry. The test host is normally one of the following: automatic test equipment (ATE), a workstation, a PC, or a microprocessor.
S TMS TDI TCK TDO U1 TMS TDI TCK TDO U2
Special Function Blocks (continued)
Start-Up Logic The start-up logic block can be configured to coordinate the relative timing of the release of GSRN, the activation of all user I/Os, and the assertion of the DONE signal at the end of configuration. If a start-up clock is used to time these events, the start-up clock can come from CCLK, or it can be routed into the startup block using upper-left corner routing resources. Temperature Sensing The built -in temperature sensing diodes allow junction temperature to be measured during device operation. A physical pin (PTEMP) is dedicated for monitoring device junction temperature. PTEMP works by forcing a 10 A current in the forward direction, and then measuring the resulting voltage. A 250 k resistor tied to 3.3 V will approximate the needed 10 A. The voltage decreases with increasing temperature at a rate of approximately -1.44 mV/C. A typical device with an 85C device temperature will measure about 640 mV. Boundary-Scan The IEEE standards 1149.1 and 1149.2 (IEEE Standard test access port and boundary-scan architecture) are implemented in the ORCA series of FPGAs. It allows users to efficiently test the interconnection between integrated circuits on a PCB as well as test the integrated circuit itself. The IEEE 1149 standard is a well-defined protocol that ensures interoperability among boundary-scan (BSCAN) equipped devices from different vendors. Series 4 FPGAs are also compliant to IEEE standard 1532/D1. This standard for boundary-scan based insystem configuration of programmable devices provides a standardized programming access and methodology for FPGAs. A device, or set of devices, implementing this standard may be programmed, read back, erased verified, singly or concurrently, with a standard set of resources. The IEEE 1149 standards define a test access port (TAP) that consists of a four-pin interface with an optional reset pin for boundary-scan testing of integrated circuits in a system. The ORCA Series FPGA provides four interface pins: test data in (TDI), test mode select (TMS), test clock (TCK), and test data out (TDO). The PRGM pin used to reconfigure the device also resets the boundary-scan logic. The user test host serially loads test commands and test data into the FPGA through these pins to drive outputs and examine inputs. In the configuration shown in Figure 26, where boundary-scan is used to test ICs, 40
net a net b net c
TDI TMS TCK TDO TMS TDI TCK TDO U3 TMS TDI TCK TDO U4
SEE ENLARGED VEIW BELOW TDO TCK TMS TDI PT[ij] TAPC BYPASS REGISTER INSTRUCTION REGISTER SCAN OUT p_ts p_out p_in PLC ARRAY p_in p_out p_ts SCAN IN BSC BDC p_in p_out SCAN IN PR[ij] DCC p_ts SCAN OUT
BSC DCC BDC PL[ij]
BSC BDC DCC
SCAN IN p_ts SCAN OUT
p_out p_in SCAN IN
SCAN OUT
BSC DCC BDC
PB[ij]
5-5972(F)
Key:BSC = boundary-scan cell, BDC = bidirectional data cell, and DCC = data control cell.
Figure 25. Printed-Circuit Board with Boundary-Scan Circuitry Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
D[7:0]
D[7:0] BOUNDARYSCAN MASTER
TDO
TDI ORCA SERIES FPGA
TDO
TDI ORCA SERIES FPGA TMS (DUT) TCK
TDO
MICROPROCESSOR
INTR
CE RA R/W DAV INT SP
TMS0 TCK (BSM) TDI
TMS (DUT) TCK
TDI ORCA SERIES FPGA TMS (DUT) TCK
TDO
5-6765(F)
Figure 26. Boundary-Scan Interface
The boundary-scan support circuit shown in Figure 26 is the 497AA boundary-scan master (BSM). The BSM off-loads tasks from the test host to increase test throughput. To interface between the test host and the DUTs, the BSM has a general MPI and provides parallel-to-serial/serial-to-parallel conversion, as well as three 8K data buffers. The BSM also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. The PC-based boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. Boundary-Scan Instructions The Series 4 boundary-scan circuitry supports a total of 18 instructions. This includes ten IEEE 1149.1, 1149.2, and 1532/D1 instructions, one optional IEEE 1149.3 instruction, two IEEE 1532/D1 optional instructions, and five ORCA-defined instructions. There are also 16 other scan chain instructions that are used only during factory device testing and will not be discussed in this data sheet. A 6-bit wide instruction register supports all the instructions listed in Table 18. The BYPASS instruction passes data intentionally from TDI to TDO after being clocked by TCK.
Table 18. Boundary-Scan Instructions Code 000000 000001 000011 000100 000101 000110 001000 001001 001010 001011 001101 001110 010001 010010 010011 010100 010101 111111 Instruction EXTEST SAMPLE PRELOAD RUNBIST IDCODE USERCODE ISC_ENABLE ISC_PROGRAM ISC_NOOP ISC_DISABLE ISC_PROGRAM_USERCODE ISC_READ PLC_SCAN_RING1 PLC_SCAN_RING2 PLC_SCAN_RING3 RAM_WRITE RAM_READ BYPASS
Lattice Semiconductor
41
ORCA Series 4 FPGAs
Data Sheet May, 2006
defined internal scan paths using the PLC latches/FFs and routing interface. The RAM_Write Enable (RAM_W) instruction allows the user to serially configure the FPGA through TDI. The RAM_Read Enable (RAM_R) allows the user to read back RAM contents on TDO after configuration. The IDCODE instruction allows the user to capture a 32-bit identification code that is unique to each device and serially output it at TDO. The IDCODE format is shown in Table 19. An optional IEEE 1149.3 instruction RUNBIST has been implemented. This instruction is used to invoke the built in self test (BIST) of regular structures like RAMs, ROMs, FIFOs, etc., and the surrounding random logic in the circuit. The USERCODE instruction shifts out a 32-bit ID serially at TDO. At powerup, a default value of the IDCODE with the manufacturer field (11-bits) set to all zeros is loaded. The user can set this 11-bit value to a userdefined number during device configuration. It may also be changed by the ISC_PROGRAM_USERCODE instruction, described later. Also implemented in Series 4 devices is the IEEE 1532/D1 standards for in-system configuration for programmable logic devices. Included are 4 mandatory and 2 optional instructions defined in the standards. ISC_ENABLE, ISC_PROGRAM, ISC_NOOP, and ISC_DISABLE are the four mandatory instructions. ISC_ENABLE initializes the devices for all subsequent ISC instructions. The ISC_PROGRAM instruction is similar to the RAM_WRITE instruction implemented in all ORCA devices where the user must monitor the PINITN pin for a high indicating the end of initialization and a successful configuration can be started. The ISC_PROGRAM instruction is used to program the configuration memory through a dedicated ISC_Pdata register. The ISC_NOOP instruction is user when programming multiple devices in parallel. During this mode TDI and TDO behave like BYPASS. The data shifted through TDI is shifted out through TDO. However the output pins remain in control of the BSR unlike BYPASS where they are driven by the system logic. The ISC_DISABLE is used upon completion of the ISC programming. No new ISC instructions will be operable without another ISC_ENABLE instruction. Optional 1532/D1 instructions include ISC_PROGRAM_USERCODE. When this instruction is loaded, the user shifts all 32-bits of a user-defined ID (LSB first) through TDI. This overwrites any ID previously loaded into the ID register. This ID can then be read back through the USERCODE instruction defined in IEEE 1149.2.
Special Function Blocks (continued)
The external test (EXTEST) instruction allows the interconnections between ICs in a system to be tested for opens and stuck-at faults. If an EXTEST instruction is performed for the system shown in Figure 25, the connections between U1 and U2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether this same value is seen at the other device. This is determined by shifting 3 bits of data for each pin (one for the output value, one for captured input value, and one for the 3-state value) through a boundary scan register (BSR) until each one aligns to the appropriate pin. Then, based upon the value of the 3-state data bit for each pin, either the I/O pad is driven to the value given in the output register of the BSR, or an input signal is applied at the pin. In either case, the BSR input register is updated with the input value from the I/O pad, which allows it to be shifted out TDO. Typically, the user will use the PRELOAD instruction to shift in the first test stimulus for the EXTEST instruction. Note that Series 4 boundary scan includes the ability to perform a selfmonitor on each I/O pin by driving out a value from the output register and checking for this value at the input register of the same I/O pad. The SAMPLE instruction is useful for system debugging and fault diagnosis by allowing the data at the FPGA's I/Os to be observed during normal operation. The data for all of the I/Os is captured simultaneously into the BSR, allowing them to be shifted-out TDO to the test host. Since each I/O buffer in the PIOs is bidirectional, two pieces of data are captured for each I/O pad: the value at the I/O pad and the value of the 3state control signal. The PRELOAD instruction is used to allow the scanning of the boundary-scan register without causing interference to the normal operation of the on-chip system logic. In turn it allows an initial data pattern to be placed at the latched parallel outputs of BSR prior to selection of another boundary scan test operation. For example, prior to selection of the EXTEST instruction, data can be loaded onto the latched parallel outputs using PRELOAD. As soon as the EXTEST instruction has been transferred to the parallel output of the instruction register, the preloaded data is driven through the system output pins. This ensures that known data, consistent at the board level, is driven immediately when the EXTEST instruction is entered. Without PRELOAD, indeterminate data would be driven until the first scan sequence had been completed. There are six ORCA-defined instructions. The PLC scan rings 1, 2, and 3 (PSR1, PSR2, PSR3) allow user42
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
ISC_READ is similar to the ORCA RAM_Read instruction which allows the user to readback the configuration RAM contents serially out on TDO. Both must monitor the PDONE signal to determine weather or not configuration is completed. ISC_READ used a 1-bit register to synchronously readback data coming from the configuration memory. The readback data is clocked into the ISC_READ data register and then clocked out TDO on the falling edge or TCK. Table 19. Series 4E Boundary-Scan Vendor-ID Codes Device OR4E02 OR4E04 OR4E06 Version(4bit) 0000 0000 0000 Part*(10bit) 0011100000 0001010000 0000110000 Family(6bit) 001000 001000 001000 Manufacturer(11bit) 00000011101 00000011101 00000011101 LSB(1bit) 1 1 1
* PLC array size of FPGA, reverse bit order. Note: Table assumes version 0.
ORCA Boundary-Scan Circuitry The ORCA Series boundary-scan circuitry includes a test access port controller (TAPC), instruction register (IR), boundary-scan register (BSR), and bypass register. It also includes circuitry to support the four predefined instructions. Figure 27 shows a functional diagram of the boundaryscan circuitry that is implemented in the ORCA Series. The input pins' (TMS, TCK, and TDI) locations vary depending on the part, and the output pin is the dedicated TDO/RD_DATA output pad. Test data in (TDI) is the serial input data. Test mode select (TMS) controls the boundary-scan test access port controller (TAPC). Test clock (TCK) is the test clock on the board. The BSR is a series connection of boundary-scan cells (BSCs) around the periphery of the IC. Each I/O pad on the FPGA, except for CCLK, DONE, and the boundaryscan pins (TCK, TDI, TMS, and TDO), is included in the BSR. The first BSC in the BSR (connected to TDI) is located in the first PIO I/O pad on the left of the top side of the FPGA (PTA PIO). The BSR proceeds clockwise around the top, right, bottom, and left sides of the array. The last BSC in the BSR (connected to TDO) is located on the top of the left side of the array (PL1D).
The bypass instruction uses a single FF, which resynchronizes test data that is not part of the current scan operation. In a bypass instruction, test data received on TDI is shifted out of the bypass register to TDO. Since the BSR (which requires a two FF delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. The boundary-scan logic is enabled before and during configuration. After configuration, a configuration option determines whether or not boundary-scan logic is used. The 32-bit boundary-scan identification register contains the manufacturer's ID number, unique part number, and version (as described earlier). The identification register is the default source for data on TDO after RESET if the TAP controller selects the shiftdata-register (SHIFT-DR) instruction. If boundary scan is not used, TMS, TDI, and TCK become user I/Os, and TDO is 3-stated or used in the readback operation.
Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
Special Function Blocks (continued)
I/O BUFFERS
DATA REGISTERS BOUNDARY-SCAN REGISTER IDCODE/USER CODE REGISTER PSR1,PSR2,PSR3 REGISTERS (PLCs) ISC READ/WRITE REGISTERS VDD CONFIGURATION REGISTER (RAM_R, RAM_W) BYPASS AND ISC_DEFAULT REGISTER DATA MUX
TDI
INSTRUCTION DECODER M U X TDO
INSTRUCTION REGISTER VDD RESET CLOCK DR SHIFT-DR UPDATE-DR RESET CLOCK IR SHIFT-IR UPDATE-IR
TMS VDD TCK VDD PRGM TAP CONTROLLER PUR
SELECT ENABLE
5-5768(F).b
Figure 27. ORCA Series Boundary-Scan Circuitry Functional Diagram ORCA Series TAP Controller (TAPC) The ORCA Series TAP controller (TAPC) is a 1149 compatible test access port controller. The 16 JTAG state assignments from the IEEE 1149 specification are used. The TAPC is controlled by TCK and TMS. The TAPC states are used for loading the IR to allow three basic functions in testing: providing test stimuli (Update-DR), test execution (Run-Test/Idle), and obtaining test responses (Capture-DR). The TAPC allows the test host to shift in and out both instructions and test data/results. The inputs and outputs of the TAPC are provided in the table below. The outputs are primarily the control signals to the instruction register and the data register. Table 20. TAP Controller Input/Outputs Symbol TMS TCK PUR
PRGM
TRESET Select Enable Capture-DR Capture-IR Shift-DR Shift-IR Update-DR Update-IR
I/O I I I I O O O O O O O O O
Function TestModeSelect TestClock PowerupReset BSCANReset TestLogicReset SelectIR(High);Select-DR(Low) TestDataOutEnable Capture/ParallelLoad-DR Capture/ParallelLoad-IR ShiftDataRegister ShiftInstructionRegister Update/ParallelLoad-DR Update/ParallelLoad-IR
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
The TAPC generates control signals that allow capture, shift, and update operations on the instruction and data registers. In the capture operation, data is loaded into the register. In the shift operation, the captured data is shifted out while new data is shifted in. In the update operation, either the instruction register is loaded for instruction decode, or the boundary-scan register is updated for control of outputs. The test host generates a test by providing input into the ORCA Series TMS input synchronous with TCK. This sequences the TAPC through states in order to perform the desired function on the instruction register or a data register. Figure 28 provides a diagram of the state transitions for the TAPC. The next state is determined by the TMS input value.
TEST-LOGICRESET 0 0 RUN-TEST/ IDLE 1 SELECTDR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECTIR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
1
5-5370(F)
Figure 28. TAP Controller State Transition Diagram Boundary-Scan Cells Figure 29 is a diagram of the boundary-scan cell (BSC) in the ORCA series PIOs. There are four BSCs in each PIC: one for each pad, except as noted above. The BSCs are connected serially to form the BSR. The BSC controls the functionality of the in, out, and 3-state signals for each I/O pad. The BSC allows the I/O to function in either the normal or test mode. Normal mode is defined as when an output buffer receives input from the PLC array and provides output at the pad or when an input buffer provides input from the pad to the PLC array. In the test mode, the BSC executes a boundary-scan operation, such as shifting in scan data from an upstream BSC in the BSR, providing test stimuli to the pad, capturing test data at the pad, etc. The primary functions of the BSC are shifting scan data serially in the BSR and observing input (p_in), output Lattice Semiconductor (p_out), and 3-state (p_ts) signals at the pads. The BSC consists of three circuits: the bidirectional data cell is used to access the input and output data, the capture cell is used to capture the status of the I/O pad, and the direction control cell is used to access the 3state value. All three cells consist of a FF used to shift scan data which feeds a FF to control the I/O buffer. The capture cell is connected serially to the bidirectional data cell, which is connected serially to the direction control cell to form a boundary-scan shift register. The TAPC signals (capture, update, shiftn, treset, and TCK) and the MODE signal control the operation of the BSC. The bidirectional data cell is also controlled by the high out/low in (HOLI) signal generated by the direction control cell. When HOLI is low, the bidirectional data cell receives input buffer data into the BSC. When HOLI is high, the BSC is loaded with functional data from the PLC.
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ORCA Series 4 FPGAs
Data Sheet May, 2006
Special Function Blocks (continued)
The MODE signal is generated from the decode of the instruction register. When the MODE signal is high (EXTEST), the scan data is propagated to the output buffer. When the MODE signal is low (BYPASS or SAMPLE), functional data from the FPGA's internal logic is propagated to the output buffer. The boundary-scan description language (BSDL) is provided for each device in the ORCA Series of FPGAs on the ispLEVER CD. The BSDL is generated from a device profile, pinout, and other boundary-scan information.
SCAN IN
CAPTURE CELL
0 1 D Q D Q
INBS (TO FPGA ARRAY)
I/O BUFFER PAD_IN P_IN BIDIRECTIONAL DATA CELL
0 D Q D Q 1
PAD_OUT
0 0 1
PAD_TS
P_OUT
1
HOLI
0 0
P_TS
D
Q
1
D
Q
1
DIRECTION CONTROL CELL
SHIFTN/CAPTURE
TCK
SCAN OUT UPDATE/TCK
MODE
5-2844(F).a
Figure 29. Boundary-Scan Cell Boundary-Scan Timing To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum frequency allowed for TCK is 20 MHz. Figure 30 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is clocked into the DUT on the rising edge. 46 Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
TEST-LOGIC-RESET SELECT-DR-SCAN SELECT-IR-SCAN RUN-TEST/IDLE RUN-TEST/IDLE
CAPTURE-IR
PAUSE-IR
TCK TMS
TDI
UPDATE-IR
SHIFT-IR
EXIT1-IR
EXIT2-IR
SHIFT-IR
EXIT1-IR
5-5971(F)
Figure 30. Instruction Register Scan Timing Diagram
Single Function Blocks
Most of the special function blocks perform a specific dedicated function. These functions are data/configuration readback control, global 3-state control (TS_ALL), internal oscillator generation, GSRN, and start-up logic. Readback Logic The readback logic can be enabled via a bit stream option or by instantiation of a library readback component. Readback is used to read back the configuration data and, optionally, the state of the PFU outputs. A readback operation can be done while the FPGA is in normal system operation. The readback operation cannot be daisy-chained. To use readback, the user selects options in the bit stream generator in the ispLEVER development system. Table 21 provides readback options selected in the bit stream generator tool. The table provides the number of times that the configuration data can be read back. This is intended primarily to give the user control over the security of the FPGA's configuration program. The user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (U).
Table 21. Readback Options Option 0 1 U Function ProhibitReadback AllowOneReadbackOnly AllowUnrestrictedNumberofReadbacks
Readback can be performed via the Series 4 MPI or by using dedicated FPGA readback controls. If the MPI is enabled, readback via the dedicated FPGA readback logic is disabled. Readback using the MPI is discussed in the MPI section. The pins used for dedicated readback are readback data (RD_DATA), read configuration (RD_CFG), and configuration clock (CCLK). A readback operation is initiated by a high-to-low transition on RD_CFG. The RD_CFG input must remain low during the readback operation. The readback operation can be restarted at frame 0 by driving the RD_CFG pin high, applying at least two rising edges of CCLK, and then driving RD_CFG low again. One bit of data is shifted out on RD_DATA at the rising edge of CCLK. The first start bit of the readback frame is transmitted out several cycles after the first rising edge of CCLK after RD_CFG is input low (see the readback timing characteristics table in the timing characteristics section). To be certain of the start of the readback frame, the data can be monitored for the 01 frame start bit pair.
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Data Sheet May, 2006
The readback frame has an identical format to that of the configuration data frame, which is discussed later in the Configuration Data Format section. If LUT memory is not used as RAM and there is no data capture, the readback data (not just the format) will be identical to the configuration data for the same frame. This eases a bitwise comparison between the configuration and readback data. The configuration header, including the length count field, is not part of the readback frame. The readback frame contains bits in locations not used in the configuration. These locations need to be masked out when comparing the configuration and readback frames. The development system optionally provides a readback bit stream to compare to readback data from the FPGA. Also note that if any of the LUTs are used as RAM and new data is written to them, these bits will not have the same values as the original configuration data frame either. Global 3-State Control (TS_ALL) To increase the testability of the ORCA Series FPGAs, the global 3-state function (TS_ALL) disables the device. The TS_ALL signal is driven from either an external pin or an internal signal. Before and during configuration, the TS_ALL signal is driven by the input pad RD_CFG. After configuration, the TS_ALL signal can be disabled, driven from the RD_CFG input pad, or driven by a general routing signal in the upper right corner. Before configuration, TS_ALL is active-low; after configuration, the sense of TS_ALL can be inverted. The following occur when TS_ALL is activated:
Special Function Blocks (continued)
Readback can be initiated at an address other than frame 0 via the new MPI control registers (see the MPI section for more information). In all cases, readback is performed at sequential addresses from the start address. It should be noted that the RD_DATA output pin is also used as the dedicated boundary-scan output pin, TDO. If this pin is being used as TDO, the RD_DATA output from readback can be routed internally to any other pin desired. The RD_CFG input pin is also used to control the global 3-state (TS_ALL) function. Before and during configuration, the TS_ALL signal is always driven by the RD_CFG input and readback is disabled. After configuration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. If used as the RD_CFG input for readback, the internal TS_ALL input can be routed internally to be driven by any input pin. The readback frame contains the configuration data and the state of the internal logic. During readback, the value of all registered PFU and PIO outputs can be captured. The following options are allowed when doing a capture of the PFU outputs.
Do not capture data (the data written to the RAMs, usually 0, will be read back). Capture data upon entering readback. Capture data based upon a configurable signal internal to the FPGA. If this signal is tied to logic 0, capture RAMs are written continuously. Capture data on either options two or three above.

All of the user I/O output buffers are 3-stated, the user I/O input buffers are pulled up (with the pulldown disabled), and the input buffers are configured with TTL input thresholds. The TDO/RD_DATA output buffer is 3-stated. The RD_CFG, RESET, and PRGM input buffers remain active with a pull-up. The DONE output buffer is 3-stated, and the input buffer is pulled up.

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ORCA Series 4 FPGAs
nects all the FPGA elements together with a standardized bus framework. The ESB facilitates communication among MPI, configuration, EBRs, and user logic in all the generic FPGA devices. AHB serves the need for high-performance system-on-chip (SoC) as well as aligning with current synthesis design flows. Multiple bus masters optimizes system performance by sharing resources between different bus masters such as the MPI and configuration logic. The wide data bus configuration of 32-bits with 4-bit parity supports the high-bandwidth of data-intensive applications of using the wide on-chip memory. AMBA enhances a reusable design methodology by defining a common backbone for IP modules. The ESB is a synchronous bus that is driven by either the MPI clock, internal oscillator, CCLK (slave configuration modes), TCK (JTAG configuration modes), or by a user clock from routing. In FPSCs, a clock from the embedded block can also drive the MPI clock. During initial configuration and reconfiguration the bus clock is defaulted to the configuration clock. The post configuration clock source is set during configuration. The user has the ability to program several slaves through the user logic interface. Embedded block RAM also interfaces seamlessly to the system bus. A single bus arbiter controls the traffic on the bus by ensuring only one master has access to the bus at any time. The arbiter monitors a number of different requests to use the bus and decides which request is currently the highest priority. The configuration modes have the highest priority and overrides all normal user modes. Priority can be programmed between MPI and user logic at configuration in generic FPGAs. If no priority is set a round-robin approach is used by granting the next requesting master in a rotating fixed order. Several interfaces exist between the ESB and other FPGA elements. The MPI interface acts as a bridge between the external microprocessor bus and ESB. The MPI may work in an independent clock domain from the ESB if the ESB clock is not sourced from the external microprocessor clock. Pipelined operation allows high-speed memory interface to the EBR and peripheral access without the requirement for additional cycles on the bus. Burst transfers allow optimal use of the memory interface by giving advance information of the nature of the transfers. Table 23 is a listing of the ESB register file and brief descriptions. Table 24 shows the system interrupt registers and Table 25 and Table 26 show the FPGA status and command registers, all with brief descriptions. More information is available in the Series 4 MPI and System Bus application note.
Microprocessor Interface (MPI)
The Series 4 FPGAs have a dedicated synchronous MPI function block. The MPI is programmable to operate with PowerPC/PowerQUICC MPC860/MPC8260 series microprocessors. The MPI implements an 8-, 16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor (PowerPC) that can be used for configuration and readback of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions. In addition to dedicated-function registers, the MPI bridges to the AMBA embedded system bus through which the PowerPC bus master can access the FPGA configuration logic, EBR and other user logic. There is also capability to interrupt the host processor either by a hard interrupt or by having the host processor poll the MPI and the embedded system bus. The control portion of the MPI is available following powerup of the FPGA if the mode pins specify MPI mode, even if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus can be 1-, 2-, or 4-bit. In configuration mode the data and parity bus width are related to the state of the M[0:3] mode pins. For postconfiguration use, the MPI must be included in the configuration bit stream by using an MPI library element in your design from the ORCA macro library, or by setting the bit of the MPI configuration control register prior to the start of configuration. The user can also enable and disable the parity bus through the configuration bit stream. These pads can be used as general I/O when they are not needed for MPI use. Table 22 shows the interface signals that are used to interface Series 4 devices to a PowerPC MPC860/ MPC8260 device. More information is available in the Series 4 MPI and System Bus application note. The ORCA FPGA is a memory-mapped peripheral to the PowerPC processor. The MPI interfaces to the user-programmable FPGA logic using the AMBA embedded system bus.The MPI has access to a series of addressable registers made accessible by the AMBA system bus that provide MPI control and status, configuration and readback data transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits wide. The address map for these registers and the user-logic address space utilize the same registers as the AMBA embedded system bus.
Embedded System Bus (ESB)
Implemented using the open standard, on-chip AMBAAHB 2.0 specification bus, the Series 4 devices conLattice Semiconductor
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Data Sheet May, 2006
Microprocessor Interface (continued)
Table 22. MPC 860 to ORCA MPI Interconnection PowerPC Signal D[0:n] DP[0:m] A[14:31] TS BURST -- -- CLKOUT RD/WR TA BDIP ORCA Pin Name D[0:n] DP[0:m] PPC_A[14:31] MPI_STRB MPI_BURST CS0 CS1 MPI_CLK MPI_RW MPI_ACK MPI_BDIP MPI I/O I/O I/O I I I I I I I O I 8, 16, 32-bit data bus. Selectable parity bus width from1, 2, and 4-bit. 32-bit MPI address bus. Transfer start signal. Active-low indicates burst transfer in-progress. High indicates current transfer not a burst. Active-low MPI select. Active-high MPI select. PowerPC interface clock. Read (high)/write (low) signal. Active-low transfer acknowledge signal. Active-low burst transfer in progress signal indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. Active-low interrupt request signal. Active-low indicates MPI detects a bus error on the internal system bus for current transaction. Requests the MPC860/MPC8260 to relinquish the bus and retry the cycle. Driven to indicate the data transfer size for the transaction (byte, half-word, word). Function
Any of IRQ[7:0] TEA RETRY TSZ[0:1]
MPI_IRQ MPI_TEA MPI_RTRY MPI_TSZ[0:1]
O O O I
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ORCA Series 4 FPGAs
Microprocessor Interface (continued)
Table 23. Embedded System Bus/MPI Registers Register 00 01 02 03 04 Byte 03-00 07-04 0B-08 0F-0C 13 12 11 10 17-14 1B-18 1F-1C 23-20 27-24 2B-28 2F-2C 33-30 37-34 3B-38 3F-3C 43--40 47--44 53--50 63--60 67--64 73--70 Read/Write Initial Value RO R/W R/W RO R/W R/W R/W RO R/W RO R/W RO RO RO RO RO RO RO RO -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Description 32-bit device ID Scratchpad register Command register Status register Interrupt enable register - MPI Interrupt enable register - USER Interrupt enable register - FPSC (unused for FPGAs) Interrupt cause register Readback address register (14 bits) Readback data register Configuration data register Trap address register Bus error address register Interrupt vector 1 predefined by configuration bit stream Interrupt vector 2 predefined by configuration bit stream Interrupt vector 3 predefined by configuration bit stream Interrupt vector 4 predefined by configuration bit stream Interrupt vector 5 predefined by configuration bit stream Interrupt vector 6 predefined by configuration bit stream Top-left PPLL Top-left HPLL Top-right PPLL Bottom-left PPLL Bottom-left HPLL Bottom-right PPLL
05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 14 18 19 1C
Note: RO = Read Only, R/W = Read/Write
Table 24. Interrupt Register Space Assignments Byte 13 12 11 10 bit 7-0 7-0 7-0 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W RO RO RO RO RO RO RO RO Description
Interrupt Enable Register - MPI Interrupt Enable Register - USER Interrupt Enable Register - FPSC Interrupt Cause Registers USER_IRQ_GENERAL; USER_IRQ_SLAVE; USER_IRQ_MASTER; CFG_IRQ_DATA; ERR_FLAG 1 MPI_IRQ FPSC_IRQ_SLAVE; FPSC_IRQ_MASTER
Note: RO = Read Only, R/W = Read/Write. For internal system bus, bit 7 is most significant bit, for MPI bit 0 is most significant bit.
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Microprocessor Interface (continued)
Table 25. Status Register Space Assignments Byte 0F 0E OD bit 7:0 7:0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Read/Write -- -- RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Description Reserved Reserved Configuration Write Data Acknowledge Readback Data Ready Unassigned (Zero) Unassigned (Zero) FPSC_BIT_ERR RAM_BIT_ERR Configuration Write Data Size (1, 2, or 4 bytes) Use with above for HSIZE[1:0] (byte, half-word, word) Readback Addresses Out of Range Error Response Received by CFG From System Bus Error Responses Received by CFG From System Bus CFG_DATA_LOST DONE INIT_N ERR_FLAG 1 ERR_FLAG 0
0C
Notes: RO = Read Only. For internal system bus, bit 7 is most significant bit, for MPI bit 0 is most significant bit.
Table 26. Command Register Space Assignments Byte 0B 0A 09 bit 7:0 7:0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved Reserved SYS_GSR (GSR Input) SYS_RD_CFG (similar to FPGA pin RD_CFGN, but active high) PRGM from MPI > (similar to FPGA pin, but active high) PRGM from USER > (similar to FPGA pin, but active high) PRGM from FPSC > (similar to FPGA pin, but active high) LOCK from MPI LOCK from USER LOCK from FPSC Bus Reset from MPI (resets system bus and registers) Bus Reset from USER (resets system bus and registers) Bus Reset from FPSC (resets system bus and registers) SYS_DAISY REPEAT_RDBK (don't increment readback address) MPI_USR_ENABLE Readback Data Size (1, 2, or 4 bytes) Use with above for HSIZE[1:0]
08
Note: R/W = Read/Write. For internal system bus; bit 7 is most significant bit, for MPI bit 0 is most significant bit.
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ORCA Series 4 FPGAs
Phase-Locked Loops (PLLs)
There are eight PLLs available to perform many clock modification and clock conditioning functions on the Series 4 FPGAs. Six of the PLLs are programmable allowing the user the flexibility to configure the PLL to manipulate the frequency, phase, and duty cycle of a clock signal. Four of the programmable PLLs (PPLLs) are capable of manipulating and conditioning clocks from 15 MHz to 200 MHz and two others (HPPLLs) are capable of manipulating and conditioning clocks from 60 MHz to 420 MHz. Frequencies can be adjusted from 1/64x to 64x the input clock frequency. Each programmable PLL provides two outputs that have different multiplication factors with the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic delay compensation mode is available for phase delay. Each PPLL and HPPLL provides two outputs that can have programmable (45 degree increments) phase differences. The PPLLs and HPPLLs can be utilized to eliminate skew between the clock input pad and the internal clock inputs across the entire device. Both the PPLLS or the HPPLLs can drive onto the primary and secondary clock networks inside the FPGA. Each can take a clock input from the dedicated pad or differential pair of pads in its corner or from general routing resources. Functionality of the PPLLs and HPPLLs is programmed during operation through a control register internal to the FPGA array or via the configuration bit stream. The embedded system bus enables access to these registers (see Table 23). There is also a PLL output signal, LOCK, that indicates a stable output clock state. Table 27. PPLL Specifications Parameter VDD15 VDD33 Operating Temp Input Clock Frequency (No division) Output Clock Frequency Min 1.425 3.0 -40 2.0 7.5 15 60 30 45 -- Nom Max Unit V V C MHz MHz % % s -- -- % degrees degrees
PPLL HPPLL PPLL HPPLL
Input Duty Cycle Output Duty Cycle Lock Time Frequency Multiplication Frequency Division Duty Cycle Adjust of Output Clock Delay Adjust of Output Clock Phase Shift Between MCLK and NCLK
1.5 1.575 3.3 3.6 -- 125 -- 200 -- 420 -- 200 -- 420 -- 70 50 55 <50 -- Up to 64x Down to 1/64x 12.5, 25, 37.5, 50, 62.5, 75, 87.5 0, 45, 90, 135, 180, 225, 270, 315 0, 45, 90, 135, 180, 225, 270, 315
Additional highly tuned and characterized dedicated phase-locked loops (DPLLs) are included to ease system designs. These DPLLs meet ITU-T G.811 primary clocking specifications and enable system designers to target very tightly specified clock conditioning not available in the programmable PPLLs. They also provide enhanced jitter filtering to reduce the amount of input jitter that is transferred to the PLL output when used in any application. DPLLs are targeted to low-speed DS1 and E1 networking systems (PLL1) and high-speed SONET/SDH networking STS-3 and STM-1 networking systems (PLL2).
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Data Sheet May, 2006
Phase-Locked Loops (continued)
Table 28. DS-1/E-1 PLL1 Specifications Parameter VDD15 VDD33 Operating Temp Input Clock Frequency Output Clock Frequency Input Duty Cycle Output Duty Cycle Lock Time Min 1.425 3.0 -40 1.0 1.0 30 47 -- Nom 1.5 3.3 -- -- -- -- 50 <1200 Max 1.575 3.6 125 2.5 2.5 70 53 -- Unit V V C MHz MHz % % s
A dedicated pin PLL_VF is needed for externally connecting a low pass filter circuit. This provides the specified DS-1/E-1 PLL operating condition.
PLL_VF
R1 C1 C2
VSS R1 = 6 k 1% C1 = 100 pF 5% C2 = 0.01 F 5%
0203(F).
Figure 31. PLL_VF External Requirements
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ORCA Series 4 FPGAs
Phase-Locked Loops (continued)
Table 29. STS-3/STM-1 PLL2 Specifications Parameter VDD15 VDD33 Operating Temp Input Clock Frequency Output Clock Frequency Input Duty Cycle Tolerance Output Duty Cycle Lock Time Min 1.425 3.0 -40 140 140 30 47 -- Nom 1.5 3.3 -- 155.52 155.52 -- 50 <50 Max 1.575 3.6 125 170 170 70 53 -- Unit V V C MHz MHz % % s
All Series 4 PLLs operate from the VDD33 power supply. Care needs to be taken during board layout to properly isolate and filter this power supply. More information about the PLLs is available in the Series 4 FPGA PLL Elements application note. The location of all eight PLLs on Series 4 FPGAs is shown in Figure 32 and Table 30.
ULPPLL ULHPPLL
URPPLL URPLL1
LLPPLL LLHPPLL
LRPPLL LRPLL2
0045(F)
Figure 32. PLL Naming Scheme Table 30. Phase-lock Loops Index Name [UL][LL][UR][LR]PPLL [UL][LL]HPPLL URPLL1 LRPLL2 Lattice Semiconductor Description Universal user programmable PLL (15--200 MHz) Universal user programmable PLL (60--420 MHz) DS-1/E-1 dedicated PLL STS-1/STM-1 dedicated PLL 55
ORCA Series 4 FPGAs
Data Sheet May, 2006
tor when initialization is complete. To synchronize the configuration of multiple FPGAs, one or more INIT pins should be wire-ANDed. If INIT is held low by one or more FPGAs or an external device, the FPGA remains in the initialization state. INIT can be used to signal that the FPGAs are not yet initialized. After INIT goes high for two internal clock cycles, the mode lines (M[3:0]) are sampled, and the FPGA enters the configuration state. The high during configuration (HDC), low during configuration (LDC), and DONE signals are active outputs in the FPGA's initialization and configuration states. HDC, LDC, and DONE can be used to provide control of external logic signals such as reset, bus enable, or PROM enable during configuration. For parallel master configuration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals.
RESET OR PRGM LOW
FPGA States of Operation
Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration, and start-up. Figure 33 outlines these three states.
POWERUP - POWER-ON TIME DELAY
INITIALIZATION - CLEAR CONFIGURATION MEMORY - INIT LOW, HDC HIGH, LDC LOW
YES
BIT ERROR
RESET, INIT, OR PRGM LOW NO
YES
NO
CONFIGURATION - M[3:0] MODE IS SELECTED - CONFIGURATION DATA FRAME WRITTEN - INIT HIGH, HDC HIGH, LDC LOW - DOUT ACTIVE
If configuration has begun, an assertion of RESET or PRGM initiates an abort, returning the FPGA to the initialization state. The PRGM and RESET pins must be pulled back high before the FPGA will enter the configuration state. During the start-up and operating states, only the assertion of PRGM causes a reconfiguration. In the master configuration modes, the FPGA is the source of configuration clock (CCLK). In this mode, the initialization state is extended to ensure that, in daisychain operation, all daisy-chained slave devices are ready. Independent of differences in clock rates, master mode devices remain in the initialization state an additional six internal clock cycles after INIT goes high. When configuration is initiated, a counter in the FPGA is set to 0 and begins to count configuration clock cycles applied to the FPGA. As each configuration data frame is supplied to the FPGA, it is internally assembled into data words. Each data word is loaded into the internal configuration memory. The configuration loading process is complete when the internal length count equals the loaded length count in the length count field, and the required end of configuration frame is written. During configuration, the PIO and PLC latches/FFs are held set/reset and the internal SLIC buffers are 3-stated. The combinatorial logic begins to function as the FPGA is configured. Figure 34 shows the general waveform of the initialization, configuration, and startup states.
START-UP - ACTIVE I/O - RELEASE INTERNAL RESET - DONE GOES HIGH PRGM LOW
OPERATION 5-4529(F).
Figure 33. FPGA States of Operation
Initialization
Upon powerup, the device goes through an initialization process. First, an internal power-on-reset circuit is triggered when power is applied. When VDD15 and VDD33 reach the voltage at which portions of the FPGA begin to operate, the I/Os are configured based on the configuration mode, as determined by the mode select inputs M[3:0]. A time-out delay is then initiated to allow the power supply voltage to stabilize. The INIT and DONE outputs are low. At the end of initialization, the default configuration option is that the configuration RAM is written to a low state. This prevents internal shorts prior to configuration. As a configuration option, after the first configuration (i.e., at reconfiguration), the user can reconfigure without clearing the internal configuration RAM first. The active-low, open-drain initialization signal INIT is released and must be pulled high by an external resis56
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ORCA Series 4 FPGAs
erly power up without any adverse effects. In cases where the power up ramps are greater than 50 mS, it is recommended that PRGM pin be held low during power up. However, this work around is only valid if the power supplies meet the above mentioned current and voltage requirements. The assertion of the PRGM will hold off the device from configuration while the device stabilizes and will not counter act any internal power up requirements.
FPGA States of Operation (continued)
Power Supply Sequencing
FPGAs are CMOS static RAM (SRAM) based programmable logic devices. The circuitry that the user designs for the FPGA is implemented within the FPGA by setting multiple SRAM configuration memory cells. This unique structure as compared with typical CMOS circuits lends to having certain powerup voltage and current requirements. This section describes these related power issues for the ORCA Series 4 FPGAs and FPSCs. The flexibility of Series 4 FPGAs lends itself to more power up considerations as it mixes many power supplies to meet today's versatile system standards. The board designer must account for the relationship of the supplies early in board development. The proper sequence of supplies insures that the board will not be troubled with power up issues. The Series 4 devices have many new design improvements to prevent short-circuit contention. This contention is typically caused by configuration RAM cells in the device not all powering up to a Q = 0 RAM state. In order for this to occur, a minimum current was needed to push the internal circuitry beyond the initial short-circuit-like condition to become a full CMOS circuit. Series 4 has overcome this requirement through many improvements which have dramatically decreased the adverse effects of internal power up memory contention. At power up, the internal VDD ramp and the duration of the ramp will depend on the amount of dynamic current available from the power supply. If a large amount of current is available, the voltage ramp seen by the device will be very fast. When final voltage has been reached, this high quiescent current is no longer required. If the available current is limited, the time for the device power to rise will be longer. The voltage ramp should be monotonic with very little or no flattening as the supply ramps up. It is also recommended that the supply should not rise and fall as it is powering up as this will cause improper power up behavior. In Series 4 devices, it is required that the VDD15 supply pass through its operational threshold voltage of approximately 1 V before the VDD33 supply reaches its operational threshold of 2.3 V. The current required by both VDD15 and VDD33 supplies while it passes through their operational thresholds is approximately between 1 and 2 amperes each. The powering of the VDDIO supplies should be after the VDD15 and VDD33 supplies reach operational levels. This sequence and supply currents can guarantee that the device will propLattice Semiconductor
Configuration
The ORCA Series FPGA functionality is determined by the state of internal configuration RAM. This configuration RAM can be loaded in a number of different modes. In these configuration modes, the FPGA can act as a master or a slave of other devices in the system. The decision as to which configuration mode to use is a system design issue. Configuration is discussed in detail, including the configuration data format and the configuration modes used to load the configuration data in the FPGA, following a description of the start-up state.
Start-Up
After configuration, the FPGA enters the start-up phase. This phase is the transition between the configuration and operational states and begins when the number of CCLKs received after INIT goes high is equal to the value of the length count field in the configuration frame and when the end of configuration frame has been written. The system design issue in the startup phase is to ensure the user I/Os become active without inadvertently activating devices in the system or causing bus contention. A second system design concern is the timing of the release of global set/reset of the PLC latches/FFs.
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FPGA States of Operation (continued)
VDD15, VDD33
RESET
PRGM INIT M[3:0] CCLK HDC LDC DONE USER I/O INTERNAL RESET (gsm) INITIALIZATION CONFIGURATION START-UP OPERATION
5-4482(F)
Figure 34. Initialization/Configuration/Start-Up Waveforms
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An example of using the synchronized modes are the CCLK_SYNC synchronized start-up mode where DONE is released on the first CCLK rising edge, C1 (see Figure 35). Since this is a synchronized start-up mode, the opendrain DONE signal can be held low externally to stop the occurrence of the other two start-up events. Once the DONE pin has been released and pulled up to a high level, the other two start-up events can be programmed individually to either happen immediately or after up to four rising edges of CCLK (Di, Di + 1, Di + 2, Di + 3, Di + 4). The default is for both events to happen immediately after DONE is released and pulled high. A commonly used design technique is to release DONE one or more clock cycles before allowing the I/O to become active. This allows other configuration devices, such as PROMs, to be disconnected using the DONE signal so that there is no bus contention when the I/Os become active. In addition to controlling the FPGA during start-up, other start-up techniques that avoid contention include using isolation devices between the FPGA and other circuits in the system, reassigning I/O locations, and maintaining I/Os as 3-stated outputs until contentions are resolved. Each of these start-up options can be selected during bit stream generation in ispLEVER, using Advanced Options. For more information, please see the ispLEVER documentation.
FPGA States of Operation (continued)
There are configuration options that control the relative timing of three events: DONE going high, release of the set/reset of internal FFs, and user I/Os becoming active. Figure 35 shows the start-up timing for ORCA FPGAs. The system designer determines the relative timing of the I/Os becoming active, DONE going high, and the release of the set/reset of internal FFs. In the ORCA Series FPGA, the three events can occur in any arbitrary sequence. This means that they can occur before or after each other, or they can occur simultaneously. There are four main start-up modes: CCLK_NOSYNC, CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC. The only difference between the modes starting with CCLK and those starting with UCLK is that for the UCLK modes, a user clock must be supplied to the start-up logic. The timing of start-up events is then based upon this user clock, rather than CCLK. The difference between the SYNC and NOSYNC modes is that for SYNC mode, the timing of two of the start-up events, release of the set/reset of internal FFs, and the I/Os becoming active is triggered by the rise of the external DONE pin followed by a variable number of rising clock edges (either CCLK or UCLK). For the NOSYNC mode, the timing of these two events is based only on either CCLK or UCLK. DONE is an open-drain bidirectional pin that may include an optional (enabled by default) pull-up resistor to accommodate wired ANDing. The open-drain DONE signals from multiple FPGAs can be tied together (ANDed) with a pull-up (internal or external) and used as an active-high ready signal, an active-low PROM enable, or a reset to other portions of the system. When used in SYNC mode, these ANDed DONE pins can be used to synchronize the other two start-up events, since they can all be synchronized to the same external signal. This signal will not rise until all FPGAs release their DONE pins, allowing the signal to be pulled high.
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FPGA States of Operation (continued)
CCLK PERIOD
F DONE C1 I/O C1 GSRN ACTIVE C1 C2 C2 C3 C3 C4 C4 C2 C3 C4
ORCA CCLK_NOSYNC
ORCA CCLK_SYNC
DONE IN DONE I/O C1, C2, C3, OR C4 Di GSRN ACTIVE Di Di + 1 Di + 1 Di + 2 Di + 2 Di + 3 Di + 3 F Di + 4 Di + 4
UCLK
ORCA UCLK_NOSYNC
F
DONE I/O C1 U1 U1 GSRN ACTIVE U1 U2 U2 U2 U3 U3 U3 U4 U4 U4
ORCA UCLK_SYNC
DONE IN DONE I/O C1 U1, U2, U3, OR U4 Di GSRN ACTIVE Di + 1 Di + 2 Di + 2 Di + 3 Di + 3 F Di + 4
Di Di + 1
UCLK PERIOD SYNCHRONIZATION UNCERTAINTY F = FINISHED, NO MORE CLKS REQUIRED.
5-2761(F)
Figure 35. Start-Up Waveforms
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ORCA Series 4 FPGAs
information on how to set these and other configuration options, please see the ispLEVER documentation.
FPGA States of Operation (continued)
Reconfiguration
To reconfigure the FPGA when the device is operating in the system, a low pulse is input into PRGM or one of the program bits in the embedded system bus control register must be set. The configuration data in the FPGA is cleared, and the I/Os not used for configuration are 3-stated with a pullup. The FPGA then samples the mode select inputs and begins reconfiguration. When reconfiguration is complete, DONE is released, allowing it to be pulled high.
Configuration Data Format
The ispLEVER Development System interfaces with front-end design entry tools and provides tools to produce a fully configured FPGA. This section discusses using the ispLEVER Development System to generate configuration RAM data and then provides the details of the configuration frame format.
Partial Reconfiguration
All ORCA device families have been designed to allow a partial reconfiguration of the FPGA at any time. This is done by setting a bit stream option in the previous configuration sequence that tells the FPGA to not reset all of the configuration RAM during a reconfiguration. Then only the configuration frames that are to be modified need to be rewritten, thereby reducing the configuration time. Other bit stream options are also available that allow one portion of the FPGA to remain in operation while a partial reconfiguration is being done. If this is done, the user must be careful to not cause contention between the two configurations (the bit stream resident in the FPGA and the partial reconfiguration bit stream) as the second reconfiguration bit stream is being loaded. During a partial re-configuration where the configuration option is set to have the internal logic remain active during configuration the internal SLJC BIDI signals will always be 3-stated. Previous families of ORCA FPGAs would allow the BIDIs to continue to be under user logic control during a partial re-configuration.
Using ispLEVER to Generate Configuration RAM Data
The configuration data bit stream defines the I/O functionality, logic, and interconnections within the FPGA. The bit stream is generated by the development system. The bit stream created by the bit stream generation tool is a series of 1s and 0s used to write the FPGA configuration RAM. It can be loaded into the FPGA using one of the configuration modes discussed later. In bit stream generator, the designer selects options that affect the FPGA's functionality. Using the output of the bit stream generator, circuit_name.bit, the development system's download tool can load the configuration data into the ORCA series FPGA evaluation board from a PC or workstation. A download cable that can be used to download from any PC or workstation supported by ispLEVER is available. This cable allows download to an FPGA that can be programmed via the serial configuration interface (requiring the mode pins to be set) or the JTAG boundary scan interface (not requiring the setting of mode pins). The lead device can then program other FPGAs or FPSCs on the board via daisy-chaining. Alternatively, a user can program a PROM (such as a Serial ROM or a standard EPROM) and load the FPGA from the PROM. The development system's PROM programming tool produces a file in .mcs, .tek or .exo format.
Other Configuration Options
There are many other configuration options available to the user that can be set during bit stream generation in ispLEVER. These include options to enable boundaryscan and/or the MPI and/or the programmable PLL blocks, readback options, and options to control and use the internal oscillator after configuration. Other useful options that affect the next configuration (not the current configuration process) include options to disable the global set/reset during configuration, disable the 3-state of I/Os during configuration, and disable the reset of internal RAMs during configuration to allow for partial configurations (see above). For more Lattice Semiconductor
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Configuration Data Format (continued)
Configuration Data Frame
Configuration data can be presented to the FPGA in two frame formats: autoincrement and explicit. A detailed description of the frame formats is shown in Figure 36, Figure 37, and Tables Table 31 and Table 31A. The two modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream size, and explicit mode uses an optional address frame. In both cases, the header frame begins with a series of 1s and a preamble of 0010, followed by a 24-bit length count field representing the total number of configuration clocks needed to complete the loading of the FPGAs. If only Series 4 devices are used, a second preamble value of 0100 is supported. If this preamble is found, the Series 4 device will expect an expanded length count field of 32bits. This allows more larger Series 4 FPGAs to be configured through daisy-chaining. Following the header frame is a mandatory ID frame. The ID frame contains data used to determine if the bit stream is being loaded to the correct type of ORCA FPGA (i.e., a bit stream generated for an OR4E06 is being sent to an OR4E06). Error checking is always enabled for Series 4 devices through the use of an 8-bit checksum. Following the ID frame is a 16-bit header to select the portion of the device to be configured with the following data. the options are an FPGA header (shown in Table 32), an embedded RAM header (shown in Table 32A), and an FPSC embedded block header (not shown). A configuration data frame follows the header frame. A data frame starts with a 01-start bit pair and ends with enough 1-stop bit to reach a byte boundary. If subsequent data frames follow the frame address is auto-incremented. If using explicit mode, an address frame can follow a data frame, telling the FPGA at what address to update the auto-increment counter to for the next data frame. Address frame starts with 00. Following all data and address frames is the postamble. The format of the postamble is the same as an address frame with the highest possible address value with the checksum set to all ones, if no other sections of configuration data follow. If another section is to follow, the header starts with 10.
CONFIGURATION DATA 0010 01 01
CONFIGURATION DATA 00
PREAMBLE LENGTH COUNT
ID FRAME
CONFIGURATION DATA FRAME 1
CONFIGURATION DATA FRAME 2
POSTAMBLE
CONFIGURATION HEADER 5-5759(F)
Figure 36. Serial Configuration Data Format--Autoincrement Mode
CONFIGURATION DATA 0010 01 00 01
CONFIGURATION DATA 00
PREAMBLE LENGTH COUNT
ID FRAME
CONFIGURATION DATA FRAME 1
ADDRESS FRAME 1
CONFIGURATION DATA FRAME 2
POSTAMBLE
CONFIGURATION HEADER 5-5760(F).a
Figure 37. Serial Configuration Data Format--Explicit Mode
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ORCA Series 4 FPGAs
Configuration Data Format (continued)
Table 31. Configuration Frame Format and Contents Frame Header Contents 11110010 24-bit length count 11111111 0101 1111 1111 1111 44 reserved bits Part ID Checksum 11111111 1111 0010 11111111 00 14-bit address Checksum 11111111 01 Alignment bits Data bits Checksum 11111111 00 or 10 11111111 111111 11111111 11111111 Description Preamble for generic FPGA. Configuration bitstream length. 8-bit trailing header. ID frame header. Reserved bits set to 0. 20-bit part ID. 8-bit checksum. 8 stop bits (high) to separate frames. This is a new mandatory header for generic portion. 8 stop bits (high) to separate frames. Address frame header. 14-bit address of generic FPGA. 8-bit checksum. Eight stop bits (high) to separate frames. Data frame header. same as generic. String of 0 bits added to frame to reach a byte boundary. Number of data bits depends upon device. 8-bit checksum. Eight stop bits (high) to separate frames. Postamble header, 00 = finish, 10 = more bits coming. Dummy address. 16 stop bits (high).
ID Frame
FPGA Header FPGA Address Frame
FPGA Data Frame
Postamble for Generic FPGA
Table 31A. Configuration Frame Format and Contents for Embedded Block RAM Frame RAM Header RAM Address Frame Contents 11110001 11111111 00 6-bit address Checksum 11111111 01 000000 512x18 data bits Checksum 11111111 00 or 10 111111 11111111 11111111 Description A mandatory header for RAM bitstream portion. 8 stop bits (high) to separate frames. Address frame header. same as generic. 6-bit address of RAM blocks. 8-bit checksum. Eight stop bits (high) to separate frames. Data frame header. same as generic. Six of 0 bits added to reach a byte boundary. Exact number of bits in a RAM block. 8-bit checksum. Eight stop bits (high) to separate frames. Postamble header. 00 = finish, 10 = more bits coming. Dummy address. 16 stop bits (high).
RAM Data Frame
Postamble for RAM
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Configuration Data Format (continued)
The number of frames, number of bits/frame, total number of bits and the required PROM size for each Series 4 device is shown in Table 32 Table 32. Configuration Frame Size Devices Number of Frames Data Bits/Frame OR4E02 1796 900 OR4E04 2436 1284 3,127,824 3,128,072 OR4E06 3076 1540 4,737,040 4,737,288
Maximum Configuration Data (Number of bits/frame x Number of frames) 1,616,400 Maximum PROM Size (bits) (add configuration header and postamble) 1,616,648
Bit Stream Error Checking
There are three different types of bit stream error checking performed in the ORCA Series 4 FPGAs: ID frame, frame alignment, and CRC checking. The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are flagged as an ID error. This frame is automatically created by the bit stream generation program in ispLEVER. Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to 1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame alignment error. Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on evaluation of the checksum byte, then a checksum/parity error is flagged. The checksum is the XOR of all the data bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and data frames. When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will remain in this state until either the RESET or PRGM pins are asserted The PGRM bits of the MPI control register can also be used to reset out of the error condition and restart configuration. If using any of the MPI modes to configure the FPGA, the specific type of bit stream error is written to one of the MPI registers by the FPGA configuration logic. This same information can also be read from the data register when in asynchronous peripheral mode.
FPGA Configuration Modes
There are twelve methods for configuring the FPGA as show in Table 33. Eleven of the configuration modes are selected on the M0, M1, M2, and M3 inputs. The twelfth configuration mode is accessed through the boundaryscan interface. Some modes are used to select the frequency of the internal oscillator, which is the source for CCLK in some configuration modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz. There are three basic FPGA configuration modes: master, slave, and peripheral which includes MPI mode. The configuration data can be transmitted to the FPGA serially or in parallel bytes. As a master, the FPGA provides the control signals out to strobe data in. As a slave device, a clock is generated externally and provided into the CCLK input. In the five peripheral modes, the FPGA acts as a microprocessor peripheral. Table 33 lists the functions of the configuration mode pins.
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Data Sheet May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
Table 33. Configuration Modes M3 0 0 0 0 1 1 1 1 1 1 1 1 M2 0 1 1 1 0 0 0 0 1 1 1 1 M1 0 0 0 1 0 0 1 1 0 0 1 1 M0 0 0 1 1 0 1 0 1 0 1 0 1 CCLK Output. High-frequency. Output. High-frequency. Output. High-frequency. NA Output. Low-frequency. Input. Output. Output. Output. Low-frequency. Output. Low-frequency. Output. Input. Configuration Mode Master Serial Master Parallel Asynchronous Peripheral Reserved Master Serial Slave Parallel MPC860 MPI MPC860 MPI Master Parallel Asynchronous Peripheral MPC860 MPI Slave Serial Data Serial 8-bit 8-bit NA Serial 8-bit 8-bit 16-bit 8-bit 8-bit 32-bit Serial
Master Parallel Mode
The master parallel configuration mode is generally used to interface to industry-standard, byte-wide memory. Figure 38 provides the connections for master parallel mode. The FPGA outputs an 22-bit address on A[21:0] to memory and reads 1 byte of configuration data on the rising edge of RCLK. The parallel bytes are internally serialized starting with the least significant bit, D0. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ispLEVER, then the user must mirror the bytes in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor.
DOUT A[17:0] A[17:0] CCLK
TO DAISYCHAINED DEVICES
D[7:0] EPROM
D[7:0] ORCA SERIES FPGA
OE CE
DONE
PROGRAM VDD
PRGM M2 M1 M0
HDC LDC RCLK
Note: M3 = GND for high-speed CCLK; M3 = VDD for low-frequency CCLK.
5-9738(F).a
Figure 38. Master Parallel Configuration Schematic In master parallel mode, the starting memory address is 00000 hex, and the FPGA increments the address for each byte loaded. Lattice Semiconductor 65
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Data Sheet May, 2006
500 ns low pulse into the FPGA's PRGM input. The FPGA's INIT input is connected to the serial ROMs' RESET/OE input, which has been programmed to function with RESET active-low and OE active-high. The FPGA DONE is routed to the CE pin. The low on DONE enables the serial ROMs. At the completion of configuration, the high on the FPGAs DONE disables the serial ROM. Serial ROMs can also be cascaded to support the configuration of multiple FPGAs or to load a single FPGA when configuration data requirements exceed the capacity of a single serial ROM. After the last bit from the first serial ROM is read, the serial ROM outputs CEO low and 3-states the DATA output. The next serial ROM recognizes the low on CE input and outputs configuration data on the DATA output. After configuration is complete, the FPGA's DONE output into CE disables the serial ROMs. This FPGA/serial ROM interface is not used in applications in which a serial ROM stores multiple configuration programs. In these applications, the next configuration program to be loaded is stored at the ROM location that follows the last address for the previous configuration program. The reason the interface in Figure 39 will not work in this application is that the low output on the INIT signal would reset the serial ROM address pointer, causing the first configuration to be reloaded. In some applications, there can be contention on the FPGA's DIN pin. During configuration, DIN receives configuration data, and after configuration, it is a user I/O. If there is contention, an early DONE at start-up (selected in ispLEVER) may correct the problem. An alternative is to use LDC to drive the serial ROM's CE pin. In order to reduce noise, it is generally better to run the master serial configuration at 1.25 MHz (M3 pin tied high), rather than 10 MHz, if possible. One FPGA in master serial mode can provide configuration data out on DOUT to additional FPGAs in a daisy-chain configuration. The configuration data on DOUT is provided synchronously with the rising edge of CCLK.
FPGA Configuration Modes (continued)
One master mode FPGA can interface to the memory and provide configuration data on DOUT to additional FPGAs in a daisy-chain. The configuration data on DOUT is provided synchronously with the rising edge of CCLK. The frequency of the CCLK output is eight times that of RCLK.
Master Serial Mode
In the master serial mode, the FPGA loads the configuration data from an external serial ROM. The configuration data is either loaded automatically at start-up or on a PRGM command to reconfigure. Serial PROMs can be used to configure the FPGA in the master serial mode. Configuration in the master serial mode can be done at powerup and/or upon a configure command. The system or the FPGA must activate the serial ROM's RESET/OE and CE inputs. At powerup, the FPGA and serial ROM each contain internal power-on reset circuitry that allows the FPGA to be configured without the system providing an external signal. The power-on reset circuitry causes the serial ROM's internal address pointer to be reset. After powerup, the FPGA automatically enters its initialization phase. The serial ROM/FPGA interface used depends on such factors as the availability of a system reset pulse, availability of an intelligent host to generate a configure command, whether a single serial ROM is used or multiple serial ROMs are cascaded, whether the serial ROM contains a single or multiple configuration programs, etc. Because of differing system requirements and capabilities, a single FPGA/serial ROM interface is generally not appropriate for all applications. Data is read in the FPGA sequentially from the serial ROM. The DATA output from the serial ROM is connected directly into the DIN input of the FPGA. The CCLK output from the FPGA is connected to the CLK input of the serial ROM. During the configuration process, CCLK clocks one data bit on each rising edge. Since the data and clock are direct connects, the FPGA/serial ROM design task is to use the system or FPGA to enable the RESET/OE and CE of the serial ROM(s). There are several methods for enabling the serial ROM's RESET/OE and CE inputs. The serial ROM's RESET/OE is programmable to function with RESET active-high and OE active-low or RESET activelow and OE active-high. In Figure 39, serial ROMs are cascaded to configure multiple daisy-chained FPGAs. The host generates a 66
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Data Sheet May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
TO DAISYCHAINED DEVICES
DATA CLK
DIN CCLK
DOUT
CE RESET/OE CEO
DONE PRGM ORCA SERIES FPGA
DATA CLK
CE RESET/OE CEO TO MORE SERIAL ROMs AS NEEDED PROGRAM
M2 M1 M0
Note: M3 = GND for high-speed CCLK; M3 = VDD for low-frequency CCLK.
5-4456(F).a
Figure 39. Master Serial Configuration Schematic
Asynchronous Peripheral Mode
Figure 40 shows the connections needed for the asynchronous peripheral mode. In this mode, the FPGA system interface is similar to that of a microprocessorperipheral interface. The microprocessor generates the control signals to write an 8-bit byte into the FPGA. The FPGA control inputs include active-low CS0 and activehigh CS1 chip selects and WR and RD inputs. The chip selects can be cycled or maintained at a static level during the configuration cycle. Each byte of data is written into the FPGA's D[7:0] input pins. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ispLEVER, then the user must mirror the bytes in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor. The FPGA provides an RDY/BUSY status output to indicate that another byte can be loaded. A low on RDY/ BUSY indicates that the double-buffered hold/shift registers are not ready to receive data, and this pin must be monitored to go high before another byte of data can be written. The shortest time RDY/BUSY is low occurs when a byte is loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the shift register. The longest time for RDY/BUSY to remain low occurs when a Lattice Semiconductor
byte is loaded into the holding register and the shift register has just started shifting configuration data into configuration RAM. The RDY/BUSY status is also available on the D7 pin by enabling the chip selects, setting WR high, and applying RD low, where the RD input provides an output enable for the D[7:3] when RD is low. The D[2:0] pins are not enabled to drive when RD is low and, therefore, only act as input pins in asynchronous peripheral mode. Optionally, the user can ignore the RDY/BUSY status and simply wait until the maximum time it would take for the RDY/BUSY line to go high, indicating the FPGA is ready for more data, before writing the next data byte. The following signals are also available on D[6:3] when WR is high and RD is low:
D[6:5] is a 2-bit configuration bitstream error description flag: 00= no error, 01 = ID error, 10 = checksum error, 11 = stop bit/frame alignment error. D[4:3] is a 2-bit system bus error flag: 00 = no error, 01 = one error occurred, 11 = multiple errors occurred.
One FPGA in asynchronous peripheral mode can provide configuration data out on DOUT to additional FPGAs in a daisy-chain configuration. The configuration data on DOUT is provided synchronously with the rising edge of CCLK. 67
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FPGA Configuration Modes (continued)
DOUT 8 PRGM D[7:0] RDY/BUSY INIT DONE CCLK
TO DAISYCHAINED DEVICES
MICROPROCESSOR ADDRESS DECODE LOGIC CS0 CS1 RD WR
ORCA SERIES FPGA
BUS CONTROLLER
VDD
M2 M1 M0
HDC LDC
Note: M3 = GND for high-speed CCLK; M3 = VDD for low-frequency CCLK.
5-9739(F).a
Figure 40. Asynchronous Peripheral Configuration
Microprocessor Interface Mode
The built-in MPI in Series 4 FPGAs is designed for use in configuring the FPGA. Figure 41 show the glueless interface for FPGA configuration and readback from the PowerPC processor. When enabled by the mode pins, the MPI handles all configuration/readback control and handshaking with the host processor. For single FPGA configuration, the host sets the configuration control register MPI_PRGM to one then back to zero and, after reading that the configuration write data acknowledge register is high, transfers data 8, 16, or 32 bits at a time to the FPGA's D[#:0] input pins. If configuring multiple FPGAs through daisy-chain operation is desired, the SYS_DAISY bit must be set in the configuration control register of the MPI. The configuration control register offers control bits to enable the interrupt on a bit stream error. The MPI status register may be used in conjunction with, or in place of, the interrupt request option. The status register contains a 2-bit field to indicate the bit stream error status. A flow chart of the MPI configuration process is shown in Figure 42.
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ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
TSZ[0:1] RETRY TEA BURST 1, 2, 4 DP[0:m] 8, 16, 32 D[0:n] A[14:31] CLKOUT RD/WR TA POWERPC BDIP IRQx TS
MPI_TSZ[0:1] MPI_RTRY MPI_TEA MPI_BURST DP[0:m] DOUT CCLK TO DAISYCHAINED DEVICES
D[0:n] PPC_A[14:31] MPI_CLK MPI_RW ORCA MPI_ACK SERIES 4 MPI_BDIP FPGA MPI_IRQ MPI_STRB DONE CS0 INIT CS1 HDC LDC
BUS CONTROLLER
5-9738(F).b
Figure 41. PowerPC/MPI Configuration Schematic Configuration readback can also be performed via the MPI when it is in user mode. The MPI is enabled in user mode by setting the MP_USER_ENABLE bit to 1 in the configuration control register prior to the start of configuration or through a configuration option. To perform readback, the host processor writes the 14-bit readback start address to the readback address registers and sets the SYS_RD_CFG bit to one, then back to zero in the configuration control register. Readback data is returned 8 bits at a time to the readback data register and is valid when the DATA_RDY bit of the status register is 1. There is no error checking during readback. A flow chart of the MPI readback operation is shown in Figure 43. The RD_DATA pin used for dedicated FPGA readback is invalid during MPI readback.
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FPGA Configuration Modes (continued)
POWER ON WITH VALID M[3:0]
WRITE CONFIGURATION CONTROL REGISTER BITS READ STATUS REGISTER
INIT = 1? YES WRITE CONFIGURATION DATA REGISTER
NO
READ STATUS REGISTER
DONE
YES
DONE = 1? NO
ERROR
YES
BIT STREAM ERROR? NO DATA_RDY = 1? YES WRITE DATA TO CONFIGURATION DATA REG NO
5-5763(F)
Figure 42. Configuration Through MPI
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ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
ENABLE MICROPROCESSOR INTERFACE IN USER MODE SET READBACK ADDRESS WRITE RD_CFG TO 0 IN CONTROL REGISTER 1 READ STATUS REGISTER
NO
DATA_RDY = 1? YES READ DATA REGISTER
ERROR
NO
DATA = 0xFF? YES READ DATA REGISTER
ERROR
NO
DATA = 0xFF? YES READ DATA REGISTER
ERROR
NO
START OF FRAME FOUND? YES READ UNTIL END OF FRAME INCREMENT ADDRESS COUNTER IN SOFTWARE
STOP
WRITE RD_CFG TO 1 IN CONTROL REGISTER 1
YES
FINISHED READBACK?
NO
5-5764(F)
Figure 43. Readback Through MPI
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FPGA Configuration Modes (continued)
Slave Serial Mode
The slave serial mode is primarily used when multiple FPGAs are configured in a daisy-chain (see the DaisyChaining section). It is also used on the FPGA evaluation board that interfaces to the download cable. A device in the slave serial mode can be used as the lead device in a daisy-chain. Figure 44 shows the connections for the slave serial configuration mode. The configuration data is provided into the FPGA's DIN input synchronous with the configuration clock CCLK input. After the FPGA has loaded its configuration data, it retransmits the incoming configuration data on DOUT at the rising edge of CCLK. CCLK is routed into all slave serial mode devices in parallel. Multiple slave FPGAs can be loaded with identical configurations simultaneously. This is done by loading the configuration data into the DIN inputs in parallel.
TO DAISYCHAINED DEVICES
DOUT
MICROPROCESSOR OR DOWNLOAD CABLE
INIT PRGM DONE CCLK DIN
ORCA SERIES FPGA
VDD M3 M2 M1 M0
HDC LDC
5-4485(F).a
Figure 44. Slave Serial Configuration Schematic
Slave Parallel Mode
The slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins D[7:0] for each CCLK cycle. Due to 8 bits of data being input per CCLK cycle, the DOUT pin does not contain a valid bit stream for slave parallel mode. As a result, the lead device cannot be used in the slave parallel mode in a daisy-chain configuration. Figure 45 is a schematic of the connections for the slave parallel configuration mode. WR and CS0 are active-low chip select signals, and CS1 is an active-high chip select signal. These chip selects allow the user to configure multiple FPGAs in slave parallel mode using an 8-bit data bus common to all of the FPGAs. These chip selects can then be used to select the FPGAs to be configured with a given bit stream. The chip selects must be active for each valid CCLK cycle until the device has been completely programmed. They can be inactive between cycles but must meet the setup and hold times for each valid positive CCLK. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ispLEVER, then the user must mirror the bytes in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor.
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ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
8
D[7:0] DONE INIT CCLK PRGM
MICROPROCESSOR OR SYSTEM
ORCA SERIES FPGA
VDD CS1 CS0 WR M3 M2 M1 M0
5-4487(F).a
HDC LDC
Figure 45. Slave Parallel Configuration Schematic
Daisy-Chaining
Multiple FPGAs can be configured by using a daisy-chain of the FPGAs. Daisy-chaining uses a lead FPGA and one or more FPGAs configured in slave serial mode. The lead FPGA can be configured in any mode except slave parallel mode. All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on positive CCLK and out on positive CCLK edges. An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received the appropriate number of data frames so that downstream FPGAs do not receive frame start indications. After loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its configuration data frames. The loading of configuration data continues after the lead device has received its configuration data if its internal frame bit counter has not reached the length count. When the configuration RAM is full and the number of bits received is less than the length count field, the FPGA shifts any additional data out on DOUT. The configuration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the positive edge of CCLK. Figure 46 shows the connections for loading multiple FPGAs in a daisy-chain configuration. The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the configuration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode and MPI mode device outputs eight CCLKs for each write cycle. If the lead device is configured in slave mode, CCLK must be routed to the lead device and to all of the daisy-chained devices.
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ORCA Series 4 FPGAs
Data Sheet May, 2006
FPGA Configuration Modes (continued)
CCLK A[17:0] EPROM D[7:0] OE CE PROGRAM D[7:0] DONE PRGM VDD M2 M1 M0 A[17:0] DOUT
CCLK DIN DOUT
CCLK DIN DOUT
ORCA SERIES FPGA MASTER
DONE INIT HDC LDC RCLK VDD PRGM M3 M2 M1 M0
ORCA SERIES FPGA SLAVE 1
DONE INIT HDC LDC RCLK VDD PRGM M3 M2 M1 M0
ORCA SERIES FPGA SLAVE 2
VDD
INIT HDC LDC RCLK VDD
5-4488(F).a
Figure 46. Daisy-Chain Configuration Schematic As seen in Figure 46, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be required, depending upon the start-up sequence desired.
Daisy-Chaining with Boundary-Scan
Multiple FPGAs can be configured through the JTAG ports by using a daisy-chain of the FPGAs. This daisy-chaining operation is available upon initial configuration after powerup, after a power-on reset, after pulling the program pin to reset the chip, or during a reconfiguration if the EN_JTAG RAM has been set. All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on the positive TCK and out on the negative TCK edges. An upstream FPGA that has received the preamble and length count outputs a high on TDO until it has received the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading and retransmitting the preamble and length count to a daisy-chain of downstream devices, the lead device loads its configuration data frames. The loading of configuration data continues after the lead device had received its configuration read into TDI of downstream devices on the positive edge of TCK, and shifted out TDO on the negative edge of TCK.
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
AbsoluteMaximumRatings
Stressesinexcessoftheabsolutemaximumratingscancausepermanentdamagetothedevice.Theseareabsolutestressratingsonly.Functionaloperationofthedeviceisnotimpliedattheseoranyotherconditionsinexcess ofthosegivenintheoperationssectionsofthisdatasheet.Exposuretoabsolutemaximumratingsforextended periodscanadverselyaffectdevicereliability. TheORCASeriesFPGAsincludecircuitrydesignedtoprotectthechipsfromdamagingsubstrateinjectioncurrents andtopreventaccumulationsofstaticcharge.Nevertheless,conventionalprecautionsshouldbeobservedduring storage,handling,andusetoavoidexposuretoexcessiveelectricalstress. Table34.AbsoluteMaximumRatings Parameter StorageTemperature PowerSupplyVoltagewithRespecttoGround Symbol Tstg VDD33 VDDIO VDD15 VIN -- -- Min -65 -0.3 -0.3 -0.3 -0.3 -0.3 -- Max 150 4.2 4.2 2.0 VDDIO+0.3 VDDIO+0.3 220 Unit C V V V V V C
InputSignalwithRespecttoGround SignalAppliedtoHigh-impedanceOutput MaximumPackageBody(Soldering)Temperature
Note: Overshoot and undershoot of -2V to (VIHMAX +2) volts is permitted for a duration of <20ns.
RecommendedOperatingConditions
Table35.RecommendedOperatingConditions Parameter PowerSupplyVoltagewithRespecttoGround Symbol VDD33 VDDIO VDD15 VIN TJ Min 3.0 1.4 1.425 -0.3 -40 Max 3.6 3.6 1.575 VDDIO+0.3 125 Unit V V V V C
InputSignalwithRespecttoGround JunctionTemperature
Note: 1. Themaximumrecommendedjunctiontemperature(TJ)duringoperationis125C. 2. TimingparametersinthisdatasheetanispLEVERarecharacterizedunderhighervoltageandtemperatureconditionsthantherecommendedoperatingconditionsinthistable. 3. TheinternalPLLsoperatefromtheVDD33powersupply.Thispowersupplyshouldbewellisolatedfromallotherpowersuppliesontheboard forproperoperation.
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Data Sheet May, 2006
ElectricalCharacteristics
Table36.ElectricalCharacteristics
OR4ExxIndustrial:VDD15=1.4Vto1.6V,VDD33=3.0Vto3.6V,VDDIO=3.0Vto3.6V,-40CParameter InputLeakageCurrent StandbyCurrent(VDD15): OR4E02 OR4E04 OR4E06 StandbyCurrent(VDD33): OR4E02 OR4E04 OR4E06 DataRetentionVoltage (VDD33) DataRetentionVoltage (VDD15) DCInputLevels DCOutputLevels OutputDriveCurrents
Symbol IL IDDSB15
TestConditions VDDIO=max,VIN=VSSorVDDIO TA=25C,VDD15=1.6V,
VDD33=3.6V,VDDIO=3.6V,
OR4Exx Min -10 -- -- -- -- -- -- -- -- 2.3 1.1 Typ -- 5 10 15 -- 4 7 10 -- -- -- -- -- -- Max 10 200 200 200 500 100 100 100 300 -- -- Various Various Various
Unit A mA mA mA mA mA mA mA mA V V V V mA
IDDSB33
internaloscillatorrunning,nooutputloads, inputsVDDIOorVSS(afterconfiguration) SameconditionsexceptTA=85C TA=25C,VDD15=1.6V,
VDD33=3.6V,VDDIO=3.6V,
VDR33 VDR15 VIL VIH VOL VOH IOL IOH CIN COUT RDONE RM IPU IPD RPU RPD
internaloscillatorstopped,nooutputloads, inputsVDDIOorGND(afterconfiguration) SameconditionsexceptTA=85C TJ=-40Cto125C TJ=-40Cto125C
InputCapacitance OutputCapacitance DONEPull-up Resistor* M[3:0]Pull-up Resistors* I/OPadStaticPull-up Current* I/OPadStatic Pull-downCurrent I/OPadPull-up Resistor* I/OPadPull-down Resistor
Inputlevelsvaryperinputstandard.Seethe Various Series4IOApplicationNotefordetails Outputlevelsvaryperoutputstandard.See Various theSeries4IOApplicationNotefordetails Outputcurrentsvaryperoutputstandard. Various SeetheSeries4IOApplicationNotefor details TA=25C,VDDIO=3.6V, -- Testfrequency=1MHz TA=25C,VDDIO=3.6V, -- Testfrequency=1MHz VDDIO=3.0Vto3.6V,VIN=VSS, 100 TJ=-40Cto125C VDDIO=3.0Vto3.6V,VIN=VSS, 100 TJ=-40Cto125C VDDIO=3.0Vto3.6V,VIN=VSS, 14.4 TJ=-40Cto125C VDDIO=3.0Vto3.6V,VIN=VSS, 26 TJ=-40Cto125C VDDIO=3.0Vto3.6V,VIN=VSS, 100 TJ=-40Cto125C VDDIO=3.0Vto3.6V,VIN=VDD, 50 TJ=-40Cto125C
-- -- -- -- -- -- -- --
5 5 -- -- 50.9 103 -- --
pF pF k k A A k k
* Thepull-upresistorwillexternallypullthepintoalevel1.0VbelowVDDIO. Note: 1.TheStandbyCurrentforVDDIOisvariabledependinguponI/Otypes.ForLVTTLI/OheldatVDDIOorGND,thisvalueistypicallyless than1mA.
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
PowerEstimation
A spreadsheet is available in ispLEVER for detailed power estimates based on circuit implementation details from ispLEVER and user inputs. A quick estimate of power dissipation for a Series 4 device is now presented.
Primary: 0.143 mW/MHz + (0.0033mW/MHz x number of blocks driven) Secondary: 0.06 mW/MHz + (0.0029mW/MHz x number of blocks driven)
Clock power is calculated from these equations by multiplying times the clock frequency in MHz. Note that an activity factor (i.e., 100% activity) is not used to calculate clock power. The device I/O power dissipated is the sum of the power dissipated in the four PIOs in the PIC. This consists of power dissipated by inputs and ac power dissipated by outputs. The power dissipated in each PIO depends on whether it is configured as an input, output, or input/output. If a PIO is operating as an output, then there is a power dissipation component for PIN, as well as POUT. This is because the output feeds back to the input. The power dissipated by a LVCMOS2 input buffer is (VIH = VDD - 0.3 V or higher) estimated as: PIN = 0.09 mW/MHz The ac power dissipation from a LVCMOS2 output or bidirectional is estimated by the following: POUT = (CL + 5.0 pF) x VDD2 x F Watts where the unit for CL (the output capacitive load) is Farads, and the unit for F is Hz. For all other I/O buffer types other than LVCMOS2, see the detailed power estimation spreadsheet available in ispLEVER.
Estimating Power Dissipation
The total operating power dissipated is estimated by adding the standby (IDDSB), internal, and external power dissipated. The internal and external power is the power consumed in the PLCs and PICs, respectively. In general, the standby power is small and may be neglected. The total operating power is as follows: PT = PINT + PIO + PCLK The internal operating power is made up of two parts: clock generation and PFU/EBR/PIO power. The PFU/ EBR/PIO power can be estimated per output based upon the number of PFU/EBR/PIO outputs switching when driving a typical fanout (three X6 lines and nine X1 lines). PINT = 0.015 mW/MHz For each PFU/EBR/PIO output that switches, 0.015 mW/MHz needs to be multiplied times the frequency (in MHz) that the output switches. Generally, this can be estimated by using the clock rate multiplied by some activity factor; for example, 20%. The power dissipated by clocks is due to either global primary clock networks or secondary/edge clock networks. Their power has a fixed component and a variable component based on the number of PFUs, PIOs, or EBRs that use that clock as follows:
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ORCA Series 4 FPGAs
Data Sheet May, 2006
TimingCharacteristics
Todefinespeedgrades,theORCAseriespartnumberdesignation(seeOrderingInformation)usesasingle-digit numbertodesignateaspeedgrade.Thisnumberisnotrelatedtoanysingleacparameter.Highernumbersindicateafastersetoftimingparameters.Theactualspeedsortingisbasedontestingthedelayinapathconsistingof aninputbuffer,combinatorialdelaythroughallPLCsinarow,andanoutputbuffer.Othertestsarethendoneto verifyotherdelayparameters,suchasroutingdelays,setuptimestoFFs,etc. ThemostaccuratetimingcharacteristicsarereportedbythetiminganalyzerinispLEVERTMdesignsoftware.A timingreportprovidedbythedevelopmentsystemafterlayoutdividespathdelaysintologicandroutingdelays. Thetiminganalyzercanalsoprovidelogicdelayspriortolayout.Whilethisallowsroutingbudgetestimates,there iswidevarianceinroutingdelaysassociatedwithdifferentlayouts. ThelogictimingparametersnotedintheElectricalCharacteristicssectionofthisdatasheetarethesameasthose inispLEVER.Inthetimingtablesthatfollow,symbolnamesaregenerallyaconcatenationofthePFUoperating mode(asdefinedinTable3)andtheparametertype.Thesetup,hold,andpropagationdelayparameters,defined below,aredesignatedinthesymbolnamebytheSET,HLD,andDELcharacters,respectively.Thevaluesgiven fortheparametersarethesameasthoseusedduringproductiontestingandspeedbinningofthedevices.The junctiontemperatureandsupplyvoltageusedtocharacterizethedevicesarelistedinthedelaytablesandthe delayvaluesinthisdatasheetarefromispLEVER.Actualdelaysatnominaltemperatureandvoltageforbest-case processescanbemuchbetterthanthevaluesgiven. Itshouldbenotedthatthejunctiontemperatureusedinthetablesisgenerally85Cor100C,basedonthetemperaturegradeofthedevice.ThejunctiontemperaturefortheFPGAdependsonthepowerdissipatedbythe device,thepackagethermalcharacteristics(JA),andtheambienttemperature,ascalculatedinthefollowing equationandasdiscussedfurtherinthePackageThermalCharacteristicssection: TJmax=TAmax+(P*JA)C Note: TheusermustdeterminethisjunctiontemperaturetoseeifthedelaysfromispLEVERshouldbederated basedonthefollowingderatingtables. Table37--Table38provideapproximatepowersupplyandjunctiontemperaturederatingforSeries4commercial andindustrialdevices.ThedelayvaluesinthisdatasheetandreportedbyispLEVERareshownas1.00inthe tables.ThemethodfordeterminingthemaximumjunctiontemperatureisdefinedinthePackageThermalCharacteristicssection.Takencumulatively,therangeofparametervaluesforbest-casevs.worst-caseprocessing,supplyvoltage,andjunctiontemperaturecanapproach3to1. ThetypicaltimingpathinSeries4ismadeupofboth3.3V(VDDIOand/orVDD33)componentsand1.5V(VDD15) components.Forexample,allI/OcircuitsuseVDDIOatthedeviceinterfacebutallinternalroutingandI/Oregister logicuseVDD15.Thusactualvoltagederatingneedstobedonebasedonmultipleparameters.Asimpleapproximationisthat50%ofthedelaypathisduetoeachoftheseparameters.AllinternalpathsuseVDD15forlogicand VDD33forrouting,butifVDD33remainsabove3.0Vtheinternaldelayscanbeassumedtobedependenton VDD15deratingvaluesonly.Notehoweverthattemperaturederatingisapproximatelythesamepercentageforall threesupplyvoltagesthusallowingonetemperaturederatingvaluetobeused.Forthemostaccurateresults,voltageandtemperaturederatingcapabilitiestobereleasedinispLEVERshouldbeused.
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Data Sheet May, 2006
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table 37. I/O Derating for 3.3 V I/Os (VDDIO)--Only valid for TTL/CMOS I/Os TJ(C) Commercial - -40 0 25 85 100 110 125 TJ(C) Industrial -40 -25 15 40 100 115 125 - PowerSupplyVoltage 3.0V 0.82 0.83 0.87 0.91 1.00 1.02 1.05 1.07 3.15V 0.80 0.81 0.84 0.88 0.97 0.99 1.01 1.03 3.3V 0.77 0.78 0.81 0.85 0.93 0.96 0.97 0.99 3.45V 0.75 0.76 0.80 0.82 0.91 0.93 0.95 0.97 3.6V 0.74 0.75 0.78 0.81 0.88 0.90 0.92 0.94
Table38.InternalDeratingfor1.5V(VDD15) TJ(C) Commercial - -40 0 25 85 100 110 125 TJ(C) Industrial -40 -25 15 40 100 115 125 - PowerSupplyVoltage 1.40V 0.87 0.89 0.93 0.96 1.02 1.04 1.05 1.06 1.425V 0.85 0.87 0.91 0.94 1.00 1.02 1.03 1.05 1.500V 0.82 0.83 0.87 0.89 0.95 0.97 0.98 1.00 1.575V 0.79 0.80 0.82 0.85 0.91 0.93 0.94 0.96 1.6V 0.78 0.79 0.81 0.84 0.90 0.92 0.93 0.95
Inadditiontosupplyvoltage,processvariation,andoperatingtemperature,circuitandprocessimprovementsof theORCASeriesFPGAsovertimewillresultinsignificantimprovementoftheactualperformanceoverthoselisted foraspeedgrade.Eventhoughlowerspeedgradesmaystillbeavailable,thedistributionofyieldtotimingparametersmaybeseveralspeedgradeshigherthanthatdesignatedonaproductbrand.Designpracticesneedtoconsiderbest-casetimingparameters(e.g.,delays=0),aswellasworst-casetiming. Theroutingdelaysareafunctionoffan-outandthecapacitanceassociatedwiththeCIPsandmetalinterconnectin thepath.Thenumberoflogicelementsthatcanbedriven(fan-out)byPFUsisunlimited,althoughthedelayto reachavalidlogiclevelcanexceedtimingrequirements.Itisdifficulttomakeaccurateroutingdelayestimatesprior todesigncompilationbasedonfan-out.ThisisbecausetheCAEsoftwaremaydeleteredundantlogicinsertedby thedesignertoreducefan-out,and/oritmayalsoautomaticallyreducefan-outbynetsplitting. ThewaveformtestpointsaregivenintheInput/OutputBufferMeasurementConditionssectionofthisdatasheet. Thetimingparametersgivenintheelectricalcharacteristicstablesinthisdatasheetfollowindustrypractices,and thevaluestheyreflectaredescribedbelow.
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ORCA Series 4 FPGAs
Data Sheet May, 2006
TimingCharacteristics(continued)
PropagationDelay--Thetimebetweenthespecifiedreferencepoints.Thedelaysprovidedaretheworstcaseof thetphhandtplldelaysfornoninvertingfunctions,tplhandtphlforinvertingfunctions,andtphzandtplzfor3-state enable. SetupTime--Theintervalimmediatelyprecedingthetransitionofaclockorlatchenablesignal,duringwhichthe datamustbestabletoensureitisrecognizedastheintendedvalue. HoldTime--Theintervalimmediatelyfollowingthetransitionofaclockorlatchenablesignal,duringwhichthe datamustbeheldstabletoensureitisrecognizedastheintendedvalue. 3-StateEnable--Thetimefromwhena3-statecontrolsignalbecomesactiveandtheoutputpadreachesthe high-impedancestate. Table 39. PFU Timing Parameters
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 C OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 C
Speed Parameter Combinatorial Delays: Four-input Variables to LUT out Five-input Variables to LUT out Six-input Variables to LUT out Sequential Delays: CLK Low Time CLK High Time Four-input Variables to Register CLK setup Five-input Variables to Register CLK setup Six-input Variables to Register CLK setup Data In to Register CLK setup Four-input Variables from Register CLK hold Five-input Variables from Register CLK hold Six-input Variables from Register CLK hold Data In from Register CLK hold Register CLK to Out PFU CLK to Out (REG_DEL) Delay Adjustments from Cycle Stealing: One Delay Cell Two Delay Cells Three Delay Cells Symbol -1 Min Max Min F4_DEL F5_DEL F6_DEL CLKL_MPW CLKH_MPW F4_SET F5_SET F6_SET DIN_SET F4_HLD F5_HLD F6_HLD DIN-HLD REG_DEL -- -- -- 0.36 0.40 0.28 0.38 0.71 0.00 0.00 0.10 0.00 0.25 1.03 0.66 0.77 1.10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.35 0.38 0.23 0.28 0.63 0.00 0.00 0.16 0.10 0.24 0.92 -2 Max 0.55 0.64 0.81 -- -- -- -- -- -- -- -- -- -- -- Min -- -- -- 0.32 0.35 0.21 0.25 0.57 0.00 0.00 0.15 0.09 0.22 0.84 -3 Max 0.50 0.58 0.74 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
CYCDEL1 CYCDEL2 CYCDEL3
0.89 1.64 2.43
-- -- --
0.70 1.29 1.98
-- -- --
0.64 1.18 1.80
-- -- --
ns ns ns
Note: A complete listing of PFU Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table40.PFUusedasDual-PortRAM:Sync.WriteandSync.orAsync.ReadTimingCharacteristics
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 C OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 C
Speed Parameter Write Operation for RAM Mode: Maximum Write Clock Frequency Write Data to CLK Setup Time Write CLK to Data Out Async Read Operation for RAM Mode: Data Out Valid After Address Sync Read Operation for RAM Mode: Maximum Read Clock Frequency Read CLK to Data Out Symbol Min SMWCLK_FRQ WD_SET MEM_DEL RA_DEL SMRCLK_FRQ REG_DEL -- 0.00 -- -- -- -- -1 Max 300.00 -- 2.21 0.66 300.00 1.03 Min -2 Max Min -3 Max 422.00 MHz -- ns 1.71 ns 0.50 ns Unit
-- 382.00 -- 0.00 -- 0.00 -- 1.89 -- -- -- -- 0.55 382.00 0.92 -- -- --
422.00 MHz 0.84 ns
Note:AcompletelistingofPFUtimingparameterscanbedisplayedinispLEVER.Thisisasamplingofthekeytimingparameters.
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ORCA Series 4 FPGAs
Data Sheet May, 2006
Timing Characteristics (continued)
Table41.EmbeddedBlockRAM(EBR)TimingCharacteristics(512x18)Quad-PortRAMMode
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 C OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 C
Speed Parameter Write Operation for RAM Mode: Maximum Write Clock Frequency Write Data to Write Clock Setup Time Write Address to Write Clock Setup Time Async Read Operation for RAM Mode: Data Out Valid After Read Address Sync Read Operation for RAM Mode: Maximum Read Clock Frequency Read Address to Read Clock Setup Time (OUTREG Mode) Read Clock to Data Out (IOREG or OUTREG modes) Symbol Min EBRWCLK_FRQ D*_CKW*_SET A*_CKW*_SET EBR_RA_DEL EBRRCLK_FRQ AR*_CKR*_SET CKR*_Q*_DEL -- 0.39 0.60 -- -- 0.59 -- -1 Max 200.0 -- -- 4.72 200.0 -- 2.39 Min -- 0.37 0.58 -- -- 0.56 -- -2 Max 217.0 -- -- 4.48 217.0 -- 2.27 Min -- 0.34 0.52 -- -- 0.51 -- -3 Max 225.0 -- -- 4.06 225.0 -- 2.06 MHz ns ns ns MHz ns ns Unit
Note: AcompletelistingofEBRTimingParameterscanbedisplayedinispLEVER.Thisisasamplingofthekeytimingparameters.
Table 42. Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 C OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 C
Speed Parameter 3-Statable BIDIs BIDI Buffer Delay BIDI 3-state Enable/Disable Delay Decoder Decoder Delay (BR[9:8], BL[9:8] to DEC) Symbol Min BUF_DEL TRI_DEL DEC_DEL -- -- -- -1 Max 0.35 0.39 0.89 -2 -3 Unit Min Max Min Max -- -- -- 0.35 0.35 0.81 -- -- -- 0.32 0.32 0.73 ns ns --
Note: AcompletelistingofSLICTimingParameterscanbedisplayedinispLEVER.Thisisasamplingofthekeytimingparameters.
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table43.PIOInputBufferTimingCharacteristics
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +85 C OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +100 C
Speed Parameter InputDelays Input Rise Time Input Fall Time Input Delay Adjustments from LVTTL: LVCMOS2 (2.5 V) LVCMOS18 (1.8 V) LVDS LVDSE LVPECL PCI_33 (3.3 V) PCI_66 (3.3 V) GTL GTLP (GTL+) HSTL_I HSTL_II HSTL_III HSTL_IV SSTL2_I SSTL2_II SSTL3_I SSTL3_II PECL Symbol Min IN_RIS IN_FAL IN_LVCMOS25 IN_LVCMOS15 IN_LVDS IN_LVDSE IN_LVPECL IN_PCI_33 IN_PCI_66 IN_GTL IN_GTLP IN_HSTL_I IN_HSTL_II IN_HSTL_III IN_HSTL_IV IN_SSTL2_I IN_SSTL2_II IN_SSTL3_I IN_SSTL3_II IN_PECL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -1 Max 100 100 0.54 1.91 -0.04 0.30 -0.31 0.59 0.59 5.32 1.87 -0.05 -0.05 -0.20 -0.20 2.28 2.28 0.78 0.78 0.83 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -2 Max 100 100 0.44 1.50 0.10 0.32 -0.21 0.50 0.50 4.68 2.04 -0.06 -0.06 -0.13 -0.13 1.66 1.66 0.69 0.69 0.72 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -3 Max 100 100 0.40 1.36 0.09 0.29 -0.19 0.45 0.45 4.26 1.86 -0.06 -0.06 -0.12 -0.12 1.51 1.51 0.63 0.63 0.65 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Notes: Thedelaysforallinputbuffersassumeaninputrise/falltimeof<1V/ns. ThevaluesintheabovetableshouldbeusedtomodifytheinformationinTable46throughTable52,whichareallbasedonLVTTLinputtiming.
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ORCA Series 4 FPGAs
Data Sheet May, 2006
TimingCharacteristics(continued)
Table44.PIOOutputBufferTimingCharacteristics
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +85 C OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +100 C
Speed Parameter OutputDelays
Output Delay Adjustments from OLVTTL_F12: LVTTL_S6 (Slew Limited, 6 mA) OUT_LVTTL_S6 -- 2.01 -- 1.72 -- LVTTL_S12 (Slew Limited, 12 mA) OUT_LVTTL_S12 -- 1.25 -- 1.06 -- LVTTL_S24 (Slew Limited, 24 mA) OUT_LVTTL_S24 -- 0.76 -- 0.60 -- LVTTL_F6 (Fast, 6 mA) OUT_LVTTL_F6 -- 0.72 -- 0.68 -- LVTTL_F24 (Fast, 24 mA) OUT_LVTTL_F24 -- -0.35 -- -0.32 -- LVCMOS18_S6 (Slew Limited, 6 mA) OUT_CMOS18_S6 -- 6.91 -- 5.36 -- LVCMOS18_S12 (Slew Limited, 12 mA) OUT_CMOS18_S12 -- 6.23 -- 3.90 -- LVCMOS18_S24 (Slew Limited, 24 mA) OUT_CMOS18_S24 -- 4.50 -- 3.29 -- LVCMOS18_F6 (Fast, 6 mA) OUT_CMOS18_F6 -- 4.75 -- 3.83 -- LVCMOS18_F12 (Fast, 12 mA) OUT_CMOS18_F12 -- 2.38 -- 1.86 -- LVCMOS18_F24 (Fast, 24 mA) OUT_CMOS18_F24 -- 1.23 -- 0.90 -- LVCMOS2_S6 (Slew Limited, 6 mA) OUT_CMOS18_S6 -- 3.26 -- 2.66 -- LVCMOS2_S12 (Slew Limited, 12 mA) OUT_CMOS18_S12 -- 2.09 -- 1.69 -- LVCMOS2_S24(Slew Limited, 24 mA) OUT_CMOS18_S24 -- 1.58 -- 1.23 -- LVCMOS2_F6 (Fast, 6 mA) OUT_CMOS18_F6 -- 1.80 -- 1.59 -- LVCMOS2_F12 (Fast, 12 mA) OUT_CMOS18_F12 -- 0.61 -- 0.50 -- LVCMOS2_F24 (Fast, 24 mA) OUT_CMOS18_F24 -- 0.03 -- -0.03 -- LVDS OUT_LVDS -- 0.07 -- 0.00 -- LVDSE OUT_LVDSE -- -0.09 -- 0.02 -- LVPECL OUT_LVPECL -- -0.57 -- -0.55 -- PCI_33 (3.3V) OUT_PCI_33 -- 4.84 -- 3.42 -- PCI_66 (3.3V) OUT_PCI_66 -- 4.84 -- 3.42 -- GTL OUT_GTL -- 3.22 -- 2.45 -- GTLP (GTL+) OUT_GTLP -- 3.60 -- 2.76 -- HSTL_I OUT_HSTL_I -- 1.89 -- 1.30 -- HSTL_II OUT_HSTL_II -- 1.89 -- 1.30 -- HSTL_III OUT_HSTL_III -- 2.78 -- 1.78 -- HSTL_IV OUT_HSTL_IV -- 2.78 -- 1.78 -- SSTL2_I OUT_SSTL2_I -- -0.15 -- -0.18 -- SSTL2_II OUT_SSTL2_II -- -0.15 -- -0.18 -- SSTL3_I OUT_SSTL3_I -- -0.50 -- -0.41 -- SSTL3_II OUT_SSTL3_II -- -0.50 -- -0.41 -- PECL OUT_PECL -- 0.12 -- 0.16 -- OutputDelayAdjustmentsfromCycleStealing(typicallyusedtoadjustsetupvs.clk->out): OneDelayCell OCYCDEL1 0.89 -- 0.70 -- 0.64 TwoDelayCells OCYCDEL2 1.64 -- 1.29 -- 1.18 ThreeDelayCells OCYCDEL3 2.43 -- 1.98 -- 1.80
* SeetheSeries4PIOApplicationnoteforoutputloadconditionsontheseoutputbuffertypes.
Symbol
-1 Min Max
-2 Min Max
-3 Min Max
Unit
Output Load (pF)
1.56 0.97 0.55 0.61 -0.29 4.87 3.55 2.99 3.48 1.69 0.82 2.42 1.54 1.12 1.44 0.45 -0.03 0.00 0.02 -0.50 3.11 3.11 2.23 2.51 1.18 1.18 1.62 1.62 -0.16 -0.16 -0.37 -0.37 0.15 -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF * * * 10 pF 10 pF * * 20 pF 20 pF 20 pF 20 pF 30 pF 30 pF 30 pF 30 pF 25 pF -- -- --
Note: ThevaluesintheabovetableshouldbeusedtomodifytheinformationinTable46throughTable48,whichareallbasedonOLVTTL_F12 outputs.
84
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table45.PrimaryClockSkewtoanyPFUorPIORegister
OR4Exx commercial/industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, -40 C < TJ < +125 C.
Speed Description PrimaryClockSkewInformation(posedgeto posedgeornegedgetonegedge) PrimaryClockSkewInformation(posedgeto posedge,negedgetonegedge,posedgeto negedgeornegedgetoposedge) Device OR4E02 OR4E04 OR4E06 OR4E02 OR4E04 OR4E06 Min -- -- -- -- -- -- -1 Max 85 110 120 265 285 300 Min -- -- -- -- -- -- -2 Max 75 95 105 190 210 220 Min -- -- -- -- -- -- -3 Max 70 90 100 180 200 210 Unit ps ps ps ps ps ps
Table46.SecondaryClocktoOutputDelaywithouton-chipPLLs(Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ< +85 C.; CL = 30 pF OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ< +100 C.; CL = 30 pF.
Speed Description SCLK OUTPUTPin(LVTTL-12mAFast, Outputwithin6PICsofSCLKinput) AdditionalDelaypereachextra6PICsper clockroutedirection. Device All All Min -- -- -1 Max 7.22 0.36 Min -- -- -2 Max 6.70 0.38 Min -- -- -3 Max 6.06 0.34 Unit ns ns
Notes: 1. Timingiswithouttheuseofthephase-lockedloops(PLLs). 2. Thisclockdelayisforafullyroutedclocktreethatusesthesecondaryclocknetwork.ItincludestheLVTTL(3.3V)inputclockbuffer,theclock routingtothePIOCLKinput,theclockQoftheFF,andthedelaythroughtheLVTTL(3.3V)dataoutputbuffer.AnSCLKinputclockcanbe atanyinputpin. 3. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferoroutputdatabuffer,seeTable53andTable55. PIOFF D Q OUTPUT(30pFLOAD)
SCLK
5-4846(F).a
Figure47.SecondaryCLKtoOutputDelay
Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
TimingCharacteristics(continued)
Table47.PrimaryCLK(PCLK)toOutputDelaywithouton-chipPLLs(Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +85 C; CL = 30 p. OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +100 C; CL = 30 p.
Speed Description PCLKInputPinOUTPUTPin(LVTTL-12mAFast) Device OR4E02 OR4E04 OR4E06 Min -- -- -- -1 Max 9.00 9.24 9.42 Min -- -- -- -2 Max 8.03 8.23 8.41 Min -- -- -- -3 Max 7.28 7.46 7.62 Unit ns ns ns
Notes: 1. Timingiswithouttheuseofthephase-lockedloops(PLLs). 2. Thisclockdelayisforafullyroutedclocktreethatusestheprimaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbufferdelay, theclockroutingtothePIOCLKinput,theclockQoftheFF,andthedelaythroughtheLVTTL(3.3V)dataoutputbuffer.ThePCLKinput clockisconnectedatthesemi-dedicatedprimaryclockinputpins. 3. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferoroutputdatabuffer,seeTable53andTable55. PIOFF D Q OUTPUT(30pFLOAD)
PCLK
5-4846(F).b
Figure 48. Primary Clock to Output Delay Table48.PrimaryCLK(PCLK)toOutputDelayusingon-chipPLLs(Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +85 C; CL = 30 p. OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +100 C; CL = 30 p.
Speed Description PCLKInputPinOUTPUTPin(LVTTL-12mAFast) Device Min OR4E02 OR4E04 OR4E06 -- -- -- -1 Max 5.53 5.54 5.53 Min -- -- -- -2 Max 5.00 5.00 5.00 Min -- -- -- -3 Max 4.54 4.55 4.54 ns ns ns Unit
PLLDelayAdjustmentsfromCycleStealing(usedto reduceclk->outbythemindelayvalueshown): OneDelayCell TwoDelayCells ThreeDelayCells
All All All
-- -- --
0.89 1.64 2.43
-- -- --
0.70 1.29 1.98
-- -- --
0.64 1.18 1.80
ns ns ns
Notes: 1. TimingusestheautomaticdelaycompensationmodeofthePLLs.ThefeedbacktothePLLisprovidedbytheglobalsystemclockrouting. OtherdelayvaluesarepossiblebyusingthephasemodificationsmodeofthePLLinstead. 2. Thisclockdelayisforafullyroutedclocktreethatusestheprimaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbufferdelay, aPLLblock,theclockroutingtothePIOCLKinput,theclockQoftheFF,andthedelaythroughtheLVTTL(3.3V)dataoutputbuffer.The PCLKinputclockisconnectedatthesemi-dedicatedPLLinputpin. 3. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferoroutputdatabuffer,seeTable53andTable55.
86
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table49.SecondaryCLK(SCLK)Setup/HoldTimewithouton-chipPLLs(Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +85 C OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +100 C
Speed Description InputtoSCLKSetupTime(Inputwithin6 PICsofSCLKinput),FastCaptureEnabled InputtoSCLKSetupTime(Inputwithin6 PICsofSCLKinput),NoInputDataDelay ReducedSetupTimepereachextra6PICs perclockroutedirection. InputtoSCLKHoldTime(Inputwithin6 PICsofSCLKinput),FastCaptureEnabled InputtoSCLKHoldTime(Inputwithin6 PICsofSCLKinput),NoInputDataDelay AdditionalHoldTimepereachextra6PICs perclockroutedirection. InputDelayAdjustmentsfromPIOCycle Stealing(typicallyusedtoreducesetuptime bytheminvalueshown): OneDelayCell TwoDelayCells ThreeDelayCells Device Min All All All All All All 5.99 0.00 0.36 0.00 3.12 0.36 -1 Max -- -- -- -- -- -- Min 5.60 0.00 0.38 0.00 3.09 0.38 -2 Max -- -- -- -- -- -- Min 5.11 0.00 0.34 0.00 2.79 0.34 -3 Max -- -- -- -- -- -- ns ns ns ns ns ns Unit
All All All
-- -- --
0.89 1.64 2.43
-- -- --
0.70 1.29 1.98
-- -- --
0.64 1.18 1.80
ns ns ns
Notes: 1. Thepin-to-pintimingparametersinthistablewillmatchispLEVERiftheclockdelaymultiplierinthesetuppreferenceissetto0.95forsetup timeand1.05forholdtime. 2. Timingiswithouttheuseofthephase-lockedloops(PLLs)orPIOinputFFcyclestealingdelays(whichcanprovidereductionsinsetuptime attheexpenseofholdtime). 3. Thissetup/holdtimeisforafullyroutedclocktreethatusesthesecondaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbuffer delay,theclockroutingtothePIOCLKinput,thesetup/holdtimeofthePIOFF(withthedatainputdelaydisabled)andthe LVTTL(3.3V)inputdatabuffertoPIOFFdelay.AnSCLKinputclockcanbeatanyinputpin. 4. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferorinputdatabuffer,seeTable53. 5. TheORT8850HFPSChasslightlyreducedperformancefromthevaluesinthistable.ispLEVERwillreporttheactualdelayvaluesforall devices,includingtheORT8850Hinthisarrangement.
PIOFF INPUT D Q
SCLK
5-4847(F).b
Figure49.InputtoSecondaryCLKSetup/HoldTime
Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
TimingCharacteristics(continued)
Table50.EdgeCLK(ECLK)Setup/HoldTimewithouton-chipPLLs(Pin-to-Pin) OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +85 C OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +100 C
Speed Description Device Min -1 Max Min -2 Max Min -3 Max Unit
Input to ECLK Setup Time (Input within 6 PICs of ECLK input), Fast Capture Enabled Input to ECLK Setup Time (Input within 6 PICs of ECLK input), Fast Input Enabled Reduced Setup Time per each extra 6 PICs per clock route direction. Input to ECLK Hold Time (Input within 6 PICs of ECLK input), Fast Capture Enabled Input to ECLK Hold Time (Input within 6 PICs of ECLK input), Fast Input Enabled Additional Hold Time per each extra 6 PICs per clock route direction. Input Delay Adjustments from PIO Cycle Stealing (typically used to reduce setup time by the min value shown): One Delay Cell Two Delay Cells Three Delay Cells
All All All All All All
1.13 0.00 0.36 0.00 1.68 0.36
-- -- -- -- -- --
1.17 0.00 0.38 0.00 1.65 0.38
-- -- -- -- -- --
1.08 0.00 0.34 0.00 1.40 0.34
-- -- -- -- -- --
ns ns ns ns ns ns
All All All
-- -- --
0.89 1.64 2.43
-- -- --
0.70 1.29 1.98
-- -- --
0.64 1.18 1.80
ns ns ns
Notes: 1. Thepin-to-pintimingparametersinthistablewillmatchispLEVERiftheclockdelaymultiplierinthesetuppreferenceissetto0.95forsetup timeand1.05forholdtime. 2. Timingiswithouttheuseofthephase-lockedloops(PLLs)orPIOinputFFcyclestealingdelays(whichcanprovidereductionsinsetuptime attheexpenseofholdtime). 3. Thissetup/holdtimeisforafullyroutedclocktreethatusestheEdgeClocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbuffer delay,theclockroutingtothePIOCLKinput,thesetup/holdtimeofthePIOFF(withthedatainputdelaydisabled)andtheLVTTL(3.3V) inputdatabuffertoPIOFFdelay.Edgeclockscanonlybeconnectedtoonepinorpin-pairperPIC,thoseendingintheletterCforsingledendedandthoseendinginCandDfordifferentialinputs.Seethepinoutsectionformoredetails. 4. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferorinputdatabuffer,seeTable53. 5. TheORT8850HFPSChasslightlyreducedperformancefromthevaluesinthistable.ispLEVERwillreporttheactualdelayvaluesforall devices,includingtheORT8850Hinthisarrangement. PIOFF INPUT D Q
ECLK
5-4847(F).b
Figure50.InputtoEdgeCLKSetup/HoldTime
88
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table51.PrimaryCLK(PCLK)Setup/HoldTimewithouton-chipPLLs(Pin-to-Pin) OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +85 C OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +100 C Description Input to PCLK Setup Time, Input Data Delay Enabled Input to PCLK Setup Time, No Input Data Delay Input to PCLK Hold Time, Input Data Delay Enabled Input to PCLK Hold Time, No Input Data Delay Input Delay Adjustments from PIO Cycle Stealing (used to reduce setup time by the min value shown): One Delay Cell Two Delay Cells Three Delay Cells Device OR4E02 OR4E04 OR4E06 OR4E02 OR4E04 OR4E06 OR4E02 OR4E04 OR4E06 OR4E02 OR4E04 OR4E06 Min 4.42 4.24 4.11 0.00 0.00 0.00 0.00 0.00 0.00 4.98 5.22 5.43 -1 Max -- -- -- -- -- -- -- -- -- -- -- -- Speed -2 Min Max 4.41 -- 4.26 -- 4.14 -- 0.00 -- 0.00 -- 0.00 -- 0.00 -- 0.00 -- 0.00 -- 4.50 -- 4.71 -- 4.89 -- -3 Min 4.04 3.90 3.80 0.00 0.00 0.00 0.00 0.00 0.00 4.07 4.26 4.42 Max -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
All All All
-- -- --
0.89 1.64 2.43
-- -- --
0.70 1.29 1.98
-- -- --
0.64 1.18 1.80
ns ns ns
Notes: 1. Thepin-to-pintimingparametersinthistablewillmatchispLEVERiftheclockdelaymultiplierinthesetuppreferenceissetto0.95forsetup timeand1.05forholdtime. 2. Timingiswithouttheuseofthephase-lockedloops(PLLs)orPIOinputFFcyclestealingdelays(whichcanprovidereductionsinsetuptime attheexpenseofholdtime). 3. Thissetup/holdtimeisforafullyroutedclocktreethatusestheprimaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbuffer delay,theclockroutingtothePIOCLKinput,thesetup/holdtimeofthePIOFF(withthedatainputdelaydisabled)andtheLVTTL(3.3V) inputdatabuffertoPIOFFdelay.ThePCLKinputclockisconnectedatthesemi-dedicatedprimaryclockinputpins. 4. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferorinputdatabuffer,seeTable53. PIOFF INPUT D Q
PCLK
5-4847(F).a
Figure51.InputtoPrimaryClockSetup/HoldTime
Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
TimingCharacteristics(continued)
Table52.PrimaryCLK(PCLK)Setup/HoldTimeusingon-chipPLLs(Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +85 C OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +100 C
Speed Description Input to PCLK Setup Time, Input Data Delay Enabled Device OR4E02 OR4E04 OR4E06 OR4E02 OR4E04 OR4E06 OR4E02 OR4E04 OR4E06 OR4E02 OR4E04 OR4E06 -1 7.92 8.01 8.08 0.00 0.00 0.00 0.00 0.00 0.00 1.55 1.56 1.57 -- -- -- -- -- -- -- -- -- -- -- -- -2 7.48 7.56 7.62 0.00 0.00 0.00 0.00 0.00 0.00 1.50 1.51 1.52 -- -- -- -- -- -- -- -- -- -- -- -- -3 6.81 6.88 6.94 0.00 0.00 0.00 0.00 0.00 0.00 1.36 1.37 1.38 -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns Min Max Min Max Min Max
Input to PCLK Setup Time, No Input Data Delay
Input to PCLK Hold Time, Input Data Delay Enabled
Input to PCLK Hold Time, No Input Data Delay
Input Delay Adjustments from PIO Cycle Stealing (typically used to reduce setup time by the min value shown): One Delay Cell Two Delay Cells Three Delay Cells PLL Delay Adjustments from Cycle Stealing (used to reduce hold by the min delay value shown): One Delay Cell Two Delay Cells Three Delay Cells
All All All
-- -- --
0.89 1.64 2.43
-- -- --
0.70 1.29 1.98
-- -- --
0.64 1.18 1.80
ns ns ns
All All All
-- -- --
0.89 1.64 2.43
-- -- --
0.70 1.29 1.98
-- -- --
0.64 1.18 1.80
ns ns ns
Notes: 1. Thepin-to-pintimingparametersinthistablewillmatchispLEVERiftheclockdelaymultiplierinthesetuppreferenceissetto0.95forsetup timeand1.05forholdtime. 2. TimingusestheautomaticdelaycompensationmodeofthePLLs.ThefeedbacktothePLLisprovidedbytheglobalsystemclockrouting. OtherdelayvaluesarepossiblebyusingthephasemodificationsmodeofthePLLinstead. 3. Thissetup/holdtimeisforafullyroutedclocktreethatusestheprimaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbuffer delay,PLLblock,theclockroutingtothePIOCLKinput,thesetup/holdtimeofthePIOFF(withthedatainputdelaydisabled)andthe LVTTL(3.3V)inputdatabuffertoPIOFFdelay.ThePCLKinputclockisconnectedatthesemi-dedicatedPLLinputpin. 4. NotethatthePIOcyclestealingdelayadjustmentsandthePLLcyclestealingdelayadjustmentsareeachattemptingtopullthesameclock inbothdirections.Ifbotharebeingused,thenthedifferencebetweenthemwillprovidethebasisforPIOsetupandholdtimes. 5. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferorinputdatabuffer,seeTable53.
90
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table53.MicroprocessorInterface(MPI)TimingCharacteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO= 3.0 V to 3.6 V, -40 C < TJ< + 125 C
Parameter MPIControl(STRB,WR,etc.)toMPI_CLKSetupTime MPIAddresstoMPI_CLKSetupTime MPIWriteDatatoMPI_CLKSetupTime AllHoldTimes MPI_CLKtoMPIControl(TA,TEA,RETRY) MPI_CLKtoMPIData(8-bit) MPI_CLKtoMPIData(16-bit) MPI_CLKtoMPIData(32-bit) MPI_CLKFrequency
Symbol MPICTRL_SET MPIADR_SET MPIDAT_SET MPI_HLD MPICTRL_DEL MPIDAT8_DEL MPIDAT16_DEL MPIDAT32_DEL MPI_CLK_FRQ
Min 7.7 3.5 3.4 0.0 -- -- -- -- --
Max -- -- -- -- 8.3 9.2 10.0 10.6 66
Unit ns ns ns ns ns ns ns ns MHz
Table54.EmbeddedSystemBus(ESB)TimingCharacteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO= 3.0 V to 3.6 V, -40 C < TJ< + 125 C
Parameter ESB_CLKFrequency(nowaitstates) ESB_CLKFrequency(withwaitstates)
Symbol ESB_CLK_FRQ ESB_CLK_FRQ
Min -- --
Max 66 100
Unit MHz MHz
Table55.Phase-LockedLoop(PLL)TimingCharacteristics See the section on PLLs in this data sheet and in the PLL application note for timing information. Table56.Boundary-ScanTimingCharacteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO= 3.0 V to 3.6 V, -40 C < TJ< +125 C; CL = 30 pF.
Parameter TDI/TMStoTCKSetupTime TDI/TMSHoldTimefromTCK TCKLowTime TCKHighTime TCKtoTDODelay TCKFrequency
Symbol TS TH TCL TCH TD TTCK
Min 10.0 0.0 25.0 25.0 -- --
Max -- -- -- -- 10.0 20.0
Unit ns ns ns ns ns MHz
TCK TS TMS TH
TDI TD TDO
Figure52.Boundary-ScanTimingDiagram
5-6764(F)
Lattice Semiconductor
91
ORCA Series 4 FPGAs
Data Sheet May, 2006
TimingCharacteristics(continued)
ConfigurationTiming
Table57.GeneralConfigurationModeTimingCharacteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +125 C;CL = 30 pF
Parameter
All Configuration Modes M[3:0] Setup Time to INIT High M[3:0] Hold Time from INIT High RESET Pulse Width Low to Start Reconfiguration PRGM Pulse Width Low to Start Reconfiguration Master and Asynchronous Peripheral Modes Power-on Reset Delay CCLK Period (M3 = 0) (M3 = 1) Configuration Latency (autoincrement mode, no EBR initialization): OR4E02 (M3 = 0) (M3 = 1) OR4E04 (M3 = 0) (M3 = 1) OR4E06 (M3 = 0) (M3 = 1) Microprocessor (MPI) Mode Power-on Reset Delay MPI Clock Period Configuration Latency (autoincrement mode, no EBR initialization): OR4E02 OR4E04 OR4E06 Partial Reconfiguration (per data frame): OR4E02 OR4E04 OR4E06 Slave Serial Mode Power-on Reset Delay CCLK Period Configuration Latency (autoincrement mode, no EBR initialization): OR4E02 OR4E04 OR4E06 Partial Reconfiguration (per data frame): OR4E02 OR4E04 OR4E06
Symbol
TSMODE THMODE TRW TPGW TPO TCCLK TCL
Min
0.00 600.00 50.00 50.00 15.70 60.00 480.00 69.7 557.6 187.7 1,501.5 284.2 2,273.9
Max
-- -- -- -- 52.40 200.00 1,600.00 232.3 1,858.6 625.6 5,004.9 947.5 7,579.7 52.40 -- -- -- -- -- -- -- 13.10 -- -- -- -- -- -- --
Unit
ns ns ns ns ms ns ns ms ms ms ms ms ms ms
TPO TCL
15.70 15.00 290,412 782,018 1,184,322
MPI clk cycles MPI clk cycles MPI clk cycles MPI clk cycles MPI clk cycles MPI clk cycles ms ns ms ms ms s s s
TPR 225 321 385 TPO TCCLK TCL 3.90 10.00 11.6 31.3 47.4 TPR 9.0 12.8 15.4
* Not applicable to asynchronous peripheral mode. Values are shown for the MPI in 32-bit mode with daisy-chaining through the DOUT pin disabled.
92
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table 58. General Configuration Mode Timing Characteristics (continued)
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, -40 C < TJ < +125 C;CL = 30 pF.
Parameter Slave Parallel Mode Power-on Reset Delay CCLK Period: Configuration Latency (normal mode): OR4E02 OR4E04 OR4E06
Symbol TPO TCCLK TCL
Min 3.90 10.00 1.5 3.9 5.9 1.1 1.6 1.9
Max 13.10 -- -- -- -- -- -- --
Unit ms ns ms ms ms s s s
Partial Reconfiguration (per data frame): TPR OR4E02 OR4E04 OR4E06 INIT Timing INIT High to CCLK Delay: TINIT_CCLK Slave Parallel Slave Serial Master Serial Master Parallel Initialization Latency (PRGM high to INIT high): TIL OR4E02 OR4E04 OR4E06 INIT High to WR, Asynchronous Peripheral TINIT_WR
Note:TPOistriggeredwhenVDD33reachesbetween2.7Vand3.0V.
0.50 0.50 0.50 0.50 0.43 0.58 0.74 2.00
1.60 1.60 1.60 1.60 1.44 1.95 2.46 --
s s s s ms ms ms s
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TimingCharacteristics(continued)
VDD15, VDD33 TPO + TIL PRGM TIL INIT TINIT_CLK TCCLK CCLK THMODE TSMODE M[3:0] TPGW
TCL DONE
5-4531(F).a
Figure53.GeneralConfigurationModeTimingDiagram
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ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table59.MasterSerialConfigurationModeTimingCharacteristics
OR4Exxcommercial/industrial:VDD15=1.4Vto1.6V,VDD33=3.0Vto3.6V,VDDIO=3.0Vto3.6V,-40CParameter DINSetupTime* DINHoldTime CCLKFrequency(M3=0) CCLKFrequency(M3=1) CCLKtoDOUTDelay
Symbol TS TH FC FC TD
Min 10.00 0.00 5.00 0.63 --
Max -- -- 16.67 2.08 5.00
Unit ns ns MHz MHz ns
Note:SerialconfigurationdataistransmittedoutonDOUTontherisingedgeofCCLKafteritisinputonDIN. * DatagetsclockedoutfromanexternalserialROM.TheclocktodatadelayoftheserialROMmustbelessthantheCCLKfrequencysince thedataavailableoutoftheserialROMmustbesetupandwaitingtobeclockedintotheFPGAbeforethenextCCLKrisingedge.
CCLK TS DIN TH BIT N TD DOUT BIT N
5-4532(F).b
Figure54.MasterSerialConfigurationModeTimingDiagram
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TimingCharacteristics(continued)
Table60.MasterParallelConfigurationModeTimingCharacteristics
OR4Exxcommercial/industrial:VDD15=1.4Vto1.6V,VDD33=3.0Vto3.6V,VDDIO=3.0Vto3.6V,-40CParameter RCLKtoAddressValid D[7:0]SetupTimetoRCLKHigh D[7:0]HoldTimetoRCLKHigh RCLKLowTime RCLKHighTime CCLKtoDOUT
Symbol TAV TS TH TCL TCH TD
Min -- 10.00 0.00 7.00 1.00 --
Max 10.00 -- -- 7.00 1.00 5.00
Unit ns ns ns CCLKcycles CCLKcycles ns
Note: TheRCLKperiodconsistsofsevenCCLKsforRCLKlowandoneCCLKforRCLKhigh. SerialdataistransmittedoutonDOUTtwoCCLKcyclesafterthebyteisinputonD[7:0].
A[21:0] TAV RCLK TS D[7:0] BYTEN TH BYTEN+1 TCH TCL
CCLK
DOUT
D0 TD
D1
D2
D3
D4
D5
D6
D7
2706(F)
Figure55.MasterParallelConfigurationModeTimingDiagram
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ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table61.AsynchronousPeripheralConfigurationModeTimingCharacteristics
OR4Exxcommercial/industrial:VDD15=1.4Vto1.6V,VDD33=3.0Vto3.6V,VDDIO=3.0Vto3.6V,-40CParameter WR,CS0,andCS1PulseWidth D[7:0]SetupTime: RDYDelay RDYLow EarliestWRAfterRDYGoesHigh RDtoD[7:0]Enable/Disable CCLKtoDOUT
Symbol TWR TS TRDY TB TWR2 TDEN TD
Min 10.00 0.00 -- 1.00 0.00 -- --
Max 60.00/500.00* -- 10.00 8.00 -- 10.00 5.00
Unit ns ns ns CCLKPeriods ns ns ns
* Thesmallerdelayisforfastasynchronousperipheralmode(modepinsM[3:0]="0101")andthelargerdelayisforslowasynchronousperipheralmode(modepinsM[3:0]="1101"). ThisparameterisvalidwhethertheendofnotRDYisdeterminedfromtheRDYpinorfromtheD7pin. Note: SerialdataistransmittedoutonDOUTontherisingedgeofCCLKafterthebyteisinputonD[7:0]. D[2:0]timingisthesameasthewritedataportionoftheD[7:3]waveformbecauseD[2:0]arenotenabledbyRD.
5-4533(F).b
CS0
CS1 TWR WR TS D[7:3] TWR2
WRITEDATA
TDEN RD
TDEN
RDY TRDY CCLK TD DOUT
PREVIOUSBYTE D7 D0 D1 D2 D3
TB
Figure56.AsynchronousPeripheralConfigurationModeTimingDiagram
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TimingCharacteristics(continued)
Table62.SlaveSerialConfigurationModeTimingCharacteristics
OR4Exxcommercial/industrial:VDD15=1.4Vto1.6V,VDD33=3.0Vto3.6V,VDDIO=3.0Vto3.6V,-40CParameter DINSetupTime DINHoldTime CCLKHighTime CCLKLowTime CCLKFrequency CCLKtoDOUT
DIN
Symbol TS TH TCH TCL FC TD
Min 5.00 0.00 5.00 5.00 -- --
Max -- -- -- -- 100.00 5.00
Unit ns ns ns ns MHz ns
Note:SerialconfigurationdataistransmittedoutonDOUTontherisingedgeofCCLKafteritisinputonDIN.
BIT N TS TH
CCLK TD DOUT TCL TCH BIT N
5-4535(F).b
Figure57.SlaveSerialConfigurationModeTimingDiagram
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ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table63.SlaveParallelConfigurationModeTimingCharacteristics
OR4Exxcommercial/industrial:VDD15=1.4Vto1.6V,VDD33=3.0Vto3.6V,VDDIO=3.0Vto3.6V,-40CParameter CS0,CS1,WRSetupTime CS0,CS1,WRHoldTime D[7:0]SetupTime D[7:0]HoldTime CCLKHighTime CCLKLowTime CCLKFrequency
Symbol TS1 TH1 TS2 TH2 TCH TCL FC
Min 5.00 2.00 5.00 0.00 5.00 5.00 --
Max -- -- -- -- -- -- 100.00
Unit ns ns ns ns ns ns MHz
Note:Daisy-chainingofFPGAsisnotsupportedinthismode.
CS0
CS1
WR TS1 TCL CCLK TS2 D[7:0]
5-2848(F)
TH1 TCH
TH2
Figure58.SlaveParallelConfigurationModeTimingDiagram
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TimingCharacteristics(continued)
ReadbackTiming
Table64.ReadbackTimingCharacteristics
OR4Exxcommercial/industrial:VDD15=1.4Vto1.6V,VDD33=3.0Vto3.6V,VDDIO=3.0Vto3.6V,-40CParameter
RD_CFGtoCCLKSetupTime RD_CFGHighWidthtoAbortReadback
CCLKLowTime CCLKHighTime CCLKFrequency CCLKtoRD_DATADelay
Symbol TS TRBA TCL TCH FC TD
Min 5.00 2 5.00 5.00 -- --
Max -- -- -- -- 100.00 5.00
Unit ns CCLKcycles ns ns MHz ns
TRBA RD_CFG TCL TS CCLK TCH TD RD_DATA BIT0 BIT1 BIT0
5-4536(F)
Figure59.ReadbackTimingDiagram
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ORCA Series 4 FPGAs
Pin Information
Pin Descriptions
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-programmable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled after configuration. The pin descriptions in Table 65 and throughout this data sheet show active-low signals with an overscore. The package pinout tables that follow, show this as a signal ending with _N, for LDC and LDC_N are equivalent. Table 65. Pin Descriptions Symbol Dedicated Pins VDD33 -- 3.3 V positive power supply. This power supply is used for 3.3 V configuration RAMs and internal PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on the board for proper operation. -- 1.5 V positive power supply for internal logic. -- Positive power supply used by I/O banks. -- Ground. I I Temperature sensing diode pin. Dedicated input. During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset. I/O Description
VDD15 VDDIO VSS PTEMP
RESET
CCLK
O In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration data in. I In the slave or readback after configuration, CCLK is input synchronous with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. As an input, a low level on DONE delays FPGA start-up after configuration.*
DONE
I
O As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has an optional pull-up resistor.
PRGM RD_CFG
I I
PRGM is an active-low input that forces the restart of configuration and resets the boundary-scan circuitry. This pin always has an active pull-up.
This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0.
RD_DATA/TDO
CFG_IRQ/MPI_IRQ
O RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary-scan, TDO is test data out. O During JTAG, slave, master, and asynchronous peripheral configuration assertion on this CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low interrupt request output, when the MPI is used.
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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Pin Information (continued)
Table 65. Pin Descriptions (continued) Symbol I/O Description
Special-Purpose Pins M[3:0] I During powerup and initialization, M0--M3 are used to select the configuration mode with their values latched on the rising edge of INIT. During configuration, a pull-up is enabled.
I/O PLL_CK[0:7][TC] I I/O P[TBLR]CLK[1:0][TC] I I/O TDI, TCK, TMS I
After configuration, these pins are user-programmable I/O.* Semi-dedicated PLL clock pins. During configuration they are 3-stated with a pull up. These pins are user-programmable I/O pins if not used by PLLs after configuration. Pins dedicated for the primary clock. Input pins on the middle of each side with differential pairing. After configuration these pins are user programmable I/O, if not used for clock inputs. Before configuration these pins are test data in, test clock, and test mode select inputs. If boundary-scan is enabled after configuration, these pins remain test data in, test clock, and test mode select inputs. If boundary-scan is not enabled after configuration, all boundery-scan functions are inhibited once configuration is complete. During configuration, either TCK or TMS must be held at a logic 1. Each pin has a pull-up enabled during configuration. To enable boundary-scan after configuration, a BNDSCAN library element must be instantiated in the user's design and the appropriate bitgen setting must be enabled in the ispLEVER software.
RDY/BUSY/RCLK
I/O After configuration, these pins are user-programmable I/O in boundary scan is not used.* O During configuration in asynchronous peripheral mode, RDY/RCLK indicates another byte can be
written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used.
HDC
I/O After configuration this pin is a user-programmable I/O pin.* O High during configuration is output high until configuration is complete. It is used as a control output,
indicating that configuration is not complete.
LDC
I/O After configuration, this pin is a user-programmable I/O pin.* O Low during configuration is output low until configuration is complete. It is used as a control output,
indicating that configuration is not complete.
INIT
I/O After configuration, this pin is a user-programmable I/O pin.* I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before the start of configuration. After configuration, this pin is a user-programmable I/O pin.*
CS0, CS1
I
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pullup is enabled.
RD/MPI_STRB
I/O After configuration, if MPI is not used, these pins are user-programmable I/O pins.* I RD is used in the asynchronous peripheral configuration mode. A low on RD changes D[7:3] into a
status output. WR and RD should not be used simultaneously. If they are, the write strobe overrides. This pin is also used as the MPI data transfer strobe. As a status indication, a high indicates ready, and a low indicates busy.
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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ORCA Series 4 FPGAs
Pin Information (continued)
Table 65. Pin Descriptions (continued) Symbol I/O Description
Special-Purpose Pins (continued) WR/MPI_RW I WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the FPGA. In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write transfer to the FPGA. I/O After configuration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.* PPC_A[14:31] I During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus master utilizing the least-significant bits of the PowerPC 32-bit address. MPI_BURST I MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high indicates that the current transfer is not a burst. I MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates MPI_BDIP that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. MPI_TSZ[0:1] I MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word. A[21:0] O During master parallel mode A[21:0] address the configuration EPROMs up to 4M bytes. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* MPI_ACK O In MPI mode this is driven low indicating the MPI received the data on the write cycle or returned data on a read cycle. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* MPI_CLK I This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a source of the clock for the embedded system bus. If MPI is used this will be the AMBA bus clock. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* MPI_TEA O A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal system bus for the current transaction. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* MPI_RTRY O This pin requests the MPC860 to relinquish the bus and retry the cycle. I/O If not used for MPI these pins are user-programmable I/O pins after configuration.* D[0:31] I/O Selectable data bus width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write transaction and driven by MPI in a read transaction. I D[7:0] receive configuration data during master parallel, peripheral, and slave parallel configuration modes when WR is low and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. O D[7:3] output internal status for asynchronous peripheral mode when RD is low. I/O After configuration, if MPI is not used, the pins are user-programmable I/O pins.* DP[0:3] I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for D[16:23], and DP[3] for D[24:31]. After configuration, if MPI is not used, the pins are user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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Pin Information (continued)
Table 65. Pin Descriptions (continued) Symbol I/O Description
Special-Purpose Pins (continued) DIN I During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a pull-up is enabled. I/O After configuration, this pin is a user-programmable I/O pin.* DOUT O During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave devices. Data out on DOUT changes on the rising edge of CCLK. I/O After configuration, DOUT is a user-programmable I/O pin.* TESTCFG I During configuration this pin should be held high, to allow configuration to occur. A pull up is enabled during configuration. I/O After configuration, TESTCFG is a user programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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ORCA Series 4 FPGAs
Pin Information (continued)
Package Compatibility
Table 66 provides the number of user I/Os available for the ORCA Series 4 FPGAs for each available package. Each package has six dedicated configuration pins. Table67thruTable69providethepackagepinandpinfunctionfortheSeries4FPGAsandpackages.Thebond padnameisidentifiedinthePIOnomeclatureusedintheispLEVERdesigneditor.TheBankcolumnprovides informationastowhichoutputvoltagelevelbankthegivenpinisin.TheGroupcolumnprovidesinformationasto thegroupofpinsthegivenpinisin.ThisisusedtoshowwhichVREFpinisusedtoprovidethereferencevoltage forsingle-endedlimited-swingI/Os.Ifnoneofthesebuffertypes(suchasSSTL,GTL,HSTL)areusedinagiven group,thentheVREFpinisavailableasanI/Opin. WhenthenumberofFPGAbondpadsexceedsthenumberofpackagepins,bondpadsareunused.Whenthe numberofpackagepinsexceedsthenumberofbondpads,packagepinsareleftunconnected(noconnects). Whenapackagepinistobeleftasanoconnectforaspecificdie,itisindicatedasanoteinthedevicecolumnfor theFPGA.Thetablesprovidenoinformationonunusedpads. Inordertoallowpin-for-pincompatibleboardlayoutsthatcanaccommodatebothdevices,somekeycompatibility issuesincludethefollowing.:
SharedControlSignalsonI/ORegisters.TheORCASeries4architecturesharesclockandcontrolsignals betweentwoadjacentI/Opads.IfI/Oregistersareused,incompatibilitiesmayarisebetweendeviceswhendifferentclockorcontrolsignalsareneededonadjacentpackagepins.Thisisbecauseonedevicemayallowindependentclockorcontrolsignalsontheseadjacentpins,whiletheothermayforcethemtobethesame.There aretwowaystoavoidthisissue. --Alwayskeepanopenbondedpin(non-bondedpinsdonotcount)betweenpinsthatrequiredifferentclockor controlsignals.NotethatthisopenpincanbeusedtoconnectsignalsthatdonotrequiretheuseofI/Oregisterstomeettiming. --Placeandroutethedesigninalltargetdevicestoverifytheyproducevaliddesigns.Notethatthismethod guaranteesthecurrentdesign,butdoesnotnecessarilyguardagainstissuesthatcanoccurwhendesign changesaremadethataffectI/Oregisters. --2X/4XI/OShiftRegisters.If2XI/Oshiftregistersor4XI/Oshiftregistersareusedinthedesign,thismay causeincompatibilitiesbetweenthedevicesbecauseonlytheAandCI/OsinaPICsupport2XI/OshiftregistersandonlyAI/Ossupports4XI/Oshiftregistermode.AandCI/Osareshowninthefollowingpinouttables undertheI/OpadcolumnsasthoseendinginAorC.
Edge Clock Input Pins. The input buffers for fast edge clocks are only available at the C I/O pad. The C I/Os are shown in the following pinout tables under the I/O pad columns as those ending in C. 680 PBGAM Differential I/O Pairs. Note that the OR4E02 device in the 680 PBGAM package has two less differential I/O pairs available than the OR4E04 or OR4E06, even though the total number of user I/Os are the same for all three devices.
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Pin Information (continued)
Table 66. ORCA Series 4 I/Os Summary Device OR4E02/OR4E04/OR4E06 User I/O Single Ended 352 PBGA 262 416 PBGAM 290 139 7 3 28 8 32 48 46/22 28/14 35/17 37/18 38/17 24/12 45/21 37/18 680 PBGAM 466 (4E4, 4E6) 405 (4E2) 197 (4E4, 4E6) 195 (4E2) 7 3 48 8 60 88 68/32 47/20 54/24 (23 for 4E2) 63/22 (21 for 4E2) 52/22 44/18 76/32 62/27
User I/O Differential Pairs (LVDS, 128 LVPECL) Configuration 7 Dedicated Function 3 VDD15 16 VDD33 8 VDDIO 24 VSS 68 Single-ended/Differential I/O per Bank Bank 0 39/19 Bank 1 26/13 Bank 2 32/16 Bank 3 33/16 Bank 4 34/16 Bank 5 24/12 Bank 6 40/19 Bank 7 34/17
Note: Each VREF pin required reduces the available user I/Os.
As shown in the Pair column, differential pairs and physical locations are numbered within each bank (e.g., L19C_A0 is the nineteenth pair in an associated bank). The C indicates complementary differential whereas a T indicates true differential. The _A0 indicates the physical location of adjacent balls in either the horizontal or vertical direction. Other physical indicators are as follows:

_A1 indicates one ball between pairs. _A2 indicates two balls between pairs. _D0 indicates balls are diagonally adjacent. _D1 indicates diagonally adjacent separated by one physical ball.
VREF pins, shown in the Additional Function column, are associated to the bank and group (e.g., VREF_TL_01 is the VREF for group one of the top left (TL) bank).
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352-Pin PBGA Pinout
Table 67. 352-Pin PBGA Pinout BA352 A1 B1 C2 AA23 C1 D2 D3 D1 E2 E4 A2 E3 E1 F2 G4 A26 F3 F1 G2 G1 G3 H2 J4 AC13 H1 H3 AA4 J2 J1 K2 J3 K1 K4 AD3 L2 K3 L1 M2 M1 VDDIO VREF Bank Group -- -- -- -- -- -- -- 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- -- -- -- -- -- -- -- 7 7 -- 7 7 8 8 -- 9 9 -- 9 9 9 9 -- 10 10 -- 10 10 1 1 1 1 -- 2 2 -- 2 2 I/O Vss VDD33 O OR4E02 OR4E04 Vss VDD33 PRD_DAT A VDD15 PRESET_ N PRD_CFG _N PPRGRM _N VDDIO0 PL2D PL2C Vss PL4D PL4C PL5D PL5C Vss PL6D PL6C VDDIO0 PL7D PL7C PL8D PL8C Vss PL10D PL10C VDD15 PL11D PL11C PL12D PL12C PL13D PL13C Vss PL14D PL14C VDDIO7 PL15D PL15C OR4E06 Vss VDD33 PRD_DAT A VDD15 PRESET_ N PRD_CFG _N PPRGRM _N VDDIO0 PL2D PL2C Vss PL4D PL4C PL6D PL6C Vss PL8D PL8C VDDIO0 PL9D PL9C PL10D PL10C Vss PL12D PL12C VDD15 PL13D PL13C PL14D PL14C PL16D PL16C Vss PL18D PL18C VDDIO7 PL19D PL19C
ORCA Series 4 FPGAs
Additional Function -- -- RD_DATA/TDO -- RESET_N RD_CFG_N PRGRM_N --
PLL_CK0C/HPPLL
Pair -- -- -- -- -- -- -- -- L12C_A1 L12T_A1 -- L13C_A1 L13T_A1 L14C_D1 L14T_D1 -- L15C_A1 L15T_A1 -- L16C_A1 L16T_A1 L17C_D1 L17T_D1 -- L18C_A1 L18T_A1 -- L19C_A0 L19T_A0 L1C_D0 L1T_D0 L2C_A2 L2T_A2 -- L3C_D0 L3T_D0 -- L4C_A0 L4T_A0 107
Vss VDD33 PRD_DA TA VDD15 VDD15 I PRESET _N I PRD_CF G_N I PPRGR M_N VDDIO0 VDDIO0 IO PL2D IO PL2C Vss Vss IO PL3D IO PL3C IO PL4D IO PL4C Vss Vss IO PL5D IO PL5C VDDIO0 VDDIO0 IO PL5B IO PL5A IO PL6D IO PL6C Vss Vss IO PL7D IO PL7C VDD15 VDD15 IO PL7B IO PL7A IO PL8D IO PL8C IO PL9D IO PL9C Vss Vss IO PL10D IO PL10C VDDIO7 VDDIO7 IO PL10B IO PL10A
PLL_CK0T/HPPLL
-- D5 D6 HDC LDC_N -- TESTCFG D7 -- VREF_0_09 A17/PPC_A31 CS0_N CS1 -- INIT_N DOUT -- VREF_0_10 A16/PPC_A30 A15/PPC_A29 A14/PPC_A28 VREF_7_01 D4 --
RDY/BUSY_N/RCLK
VREF_7_02 -- A13/PPC_A27 A12/PPC_A26
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout BA352 AE1 L3 N2 AC11 M4 N1 AE2 M3 P2 P4 AC16 AE25 P1 N3 AF1 R2 P3 R1 T2 AF25 R3 T1 R4 U2 T3 U1 U4 V2 U3 V1 W2 W1 V3 Y2 W4 Y1 W3 B25 AA2 Y4 AA1 Y3 AB2 AB1 108 VDDIO VREF Bank Group -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) -- -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 3 3 -- 4 4 -- 4 4 -- -- -- 5 5 -- 5 5 6 6 -- 6 6 6 6 -- 7 7 8 8 8 8 8 8 8 8 1 1 -- 1 1 2 -- 3 3 I/O Vss IO IO VDD15 IO IO Vss IO IO VDDIO7 VDD15 Vss IO IO Vss IO IO IO IO Vss IO IO IO IO VDDIO7 IO IO IO IO IO IO IO IO IO IO IO IO Vss IO IO IO VDDIO6 IO IO OR4E02 Vss PL11B PL11A VDD15 PL13D PL13C Vss PL14D PL14C VDDIO7 VDD15 Vss PL15D PL15C Vss PL16D PL16C PL17D PL17C Vss PL17B PL17A PL18D PL18C VDDIO7 PL19D PL19C PL20D PL20C PL20B PL20A PL21D PL21C PL21B PL21A PL22D PL22C Vss PL22B PL22A PL23C VDDIO6 PL24D PL24C OR4E04 Vss PL17D PL17C VDD15 PL19D PL19C Vss PL20D PL20C VDDIO7 VDD15 Vss PL21D PL21C Vss PL22D PL22C PL24D PL24C Vss PL25D PL25C PL26D PL26C VDDIO7 PL27D PL27C PL28D PL28C PL29D PL29C PL30D PL30C PL31D PL31C PL32D PL32C Vss PL33D PL33C PL34C VDDIO6 PL35B PL35A OR4E06 Vss PL21D PL21C VDD15 PL23D PL23C Vss PL24D PL24C VDDIO7 VDD15 Vss PL25D PL25C Vss PL26D PL26C PL28D PL28C Vss PL29D PL29C PL30D PL30C VDDIO7 PL32D PL32C PL34D PL34C PL35D PL35C PL36D PL36C PL37D PL37C PL38D PL38C Vss PL39D PL39C PL40C VDDIO6 PL42D PL42C Additional Function -- A11/PPC_A25 VREF_7_03 --
RD_N/MPI_STRB_N
Data Sheet May, 2006
Pair -- L5C_D1 L5T_D1 -- L6C_D2 L6T_D2 -- L7C_D1 L7T_D1 -- -- -- L8C_D1 L8T_D1 -- L9C_D0 L9T_D0 L10C_D0 L10T_D0 -- L11C_D1 L11T_D1 L12C_D1 L12T_D1 -- L13C_A2 L13T_A2 L14C_D1 L14T_D1 L15C_D0 L15T_D0 L16C_D1 L16T_D1 L17C_D1 L17T_D1 L1C_D1 L1T_D1 -- L2C_D1 L2T_D1 -- -- L3C_A0 L3T_A0 Lattice Semiconductor
VREF_7_04 -- PLCK0C PLCK0T -- -- -- A10/PPC_A24 A9/PPC_A23 -- A8/PPC_A22 VREF_7_05 PLCK1C PLCK1T -- VREF_7_06 A7/PPC_A21 A6/PPC_A20 A5/PPC_A19 -- WR_N/MPI_RW VREF_7_07 A4/PPC_A18 VREF_7_08 A3/PPC_A17 A2/PPC_A16 A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 -- D9 D10 VREF_6_02 -- D11 D12
Data Sheet May, 2006
Table 67. 352-Pin PBGA Pinout BA352 B26 AA3 AC2 C24 AB4 AC1 C3 D14 AB3 AD2 AC21 AC3 AD1 D19 AF2 AC6 AE3 AF3 AE4 AD4 AF4 D23 AE5 AC5 AD5 AF5 AE6 AC7 AD6 D4 AF6 AE7 AF7 AD7 AE8 AC9 D9 AF8 AD8 AE9 AF9 AE10 AD9 AF10 VDDIO VREF Bank Group -- 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) -- -- -- 6 (BL) -- -- -- -- -- -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 3 3 -- 4 4 -- -- -- -- -- -- -- -- -- -- 5 5 5 5 5 -- 6 6 -- 7 7 7 7 -- 7 7 8 8 8 8 -- 9 9 9 9 10 10 -- I/O OR4E02 OR4E04 Vss PL36B PL36A Vss PL39D PL39C Vss Vss PTEMP VDDIO6 VDD15 LVDS_R VDD33 Vss VDD33 VDD15 PB2A PB2C PB2D PB4A PB4B Vss PB5C PB5D VDDIO6 PB6C PB6D PB7C PB7D Vss PB8C PB8D PB9C PB9D PB10C PB10D Vss PB11C PB11D PB12C PB12D PB13C PB13D VDDIO6 OR4E06 Vss PL44D PL44C Vss PL47D PL47C Vss Vss PTEMP VDDIO6 VDD15 LVDS_R VDD33 Vss VDD33 VDD15 PB2A PB2C PB2D PB4C PB4D Vss PB6C PB6D VDDIO6 PB8C PB8D PB9C PB9D Vss PB10C PB10D PB11C PB11D PB12C PB12D Vss PB13C PB13D PB14C PB14D PB16C PB16D VDDIO6
ORCA Series 4 FPGAs
Additional Function -- VREF_6_03 D13 --
PLL_CK7C/HPPLL
Pair -- L4C_D1 L4T_D1 -- L5C_D2 L5T_D2 -- -- -- -- -- -- -- -- -- -- -- L6T_A0 L6C_A0 L7T_A1 L7C_A1 -- L8T_A1 L8C_A1 -- L9T_D0 L9C_D0 L10T_D0 L10C_D0 -- L11T_D0 L11C_D0 L12T_A1 L12C_A1 L13T_D1 L13C_D1 -- L14T_A1 L14C_A1 L15T_A0 L15C_A0 L16T_D0 L16C_D0 -- 109
Vss Vss IO PL25D IO PL25C Vss Vss IO PL27D IO PL27C Vss Vss Vss Vss I PTEMP VDDIO6 VDDIO6 VDD15 VDD15 IO LVDS_R VDD33 VDD33 Vss Vss VDD33 VDD33 VDD15 VDD15 IO PB2A IO PB2C IO PB2D IO PB3C IO PB3D Vss Vss IO PB4C IO PB4D VDDIO6 VDDIO6 IO PB5C IO PB5D IO PB6A IO PB6B Vss Vss IO PB6C IO PB6D IO PB7A IO PB7B IO PB7C IO PB7D Vss Vss IO PB8C IO PB8D IO PB9C IO PB9D IO PB10C IO PB10D VDDIO6 VDDIO6
PLL_CK7T/HPPLL
-- -- PTEMP -- -- LVDS_R -- -- -- -- DP2
PLL_CK6T/PPLL PLL_CK6C/PPLL
VREF_6_05 DP3 -- VREF_6_06 D14 -- D15 D16 D17 D18 -- VREF_6_07 D19 D20 D21 VREF_6_08 D22 -- D23 D24 VREF_6_09 D25 D26 D27 --
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout BA352 AC10 AE11 AD10 AF11 AE12 AF12 AD11 AE13 D11 AC12 AF13 H4 AD12 AE14 AC14 AF14 AD13 D16 AE15 AD14 AF15 AE16 J23 AD15 AF16 AC15 AE17 AD16 AF17 AC17 N4 P23 AE18 AD17 AF18 AE19 AF19 AD18 AE20 AC19 L13 AF20 AD19 AE21 110 VDDIO VREF Bank Group 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 10 10 11 11 11 11 1 1 -- 1 1 -- 2 2 -- 2 2 -- 3 3 3 3 -- 3 3 4 4 -- 4 4 -- -- 5 5 5 5 6 6 1 1 -- 1 1 1 I/O IO IO IO IO IO IO IO IO VDD15 IO IO Vss IO IO VDDIO5 IO IO VDD15 IO IO IO IO Vss IO IO IO IO VDDIO5 IO IO Vss Vss IO IO IO IO IO IO IO IO Vss IO IO IO OR4E02 PB11C PB11D PB12A PB12B PB12C PB12D PB13A PB13B VDD15 PB13C PB13D Vss PB14C PB14D VDDIO5 PB15C PB15D VDD15 PB16C PB16D PB17A PB17B Vss PB17C PB17D PB18A PB18B VDDIO5 PB18C PB18D Vss Vss PB19C PB19D PB20C PB20D PB21A PB21B PB22A PB22B Vss PB22C PB22D PB23A OR4E04 PB14C PB14D PB15C PB15D PB16C PB16D PB17C PB17D VDD15 PB18C PB18D Vss PB19C PB19D VDDIO5 PB20C PB20D VDD15 PB21C PB21D PB22C PB22D Vss PB23C PB23D PB24C PB24D VDDIO5 PB25C PB25D Vss Vss PB26C PB26D PB27C PB27D PB28C PB28D PB30C PB30D Vss PB31C PB31D PB32C OR4E06 PB18C PB18D PB19C PB19D PB20C PB20D PB21C PB21D VDD15 PB22C PB22D Vss PB23C PB23D VDDIO5 PB24C PB24D VDD15 PB26C PB26D PB27C PB27D Vss PB28C PB28D PB29C PB29D VDDIO5 PB30C PB30D Vss Vss PB32C PB32D PB34C PB34D PB35C PB35D PB37C PB37D Vss PB38C PB38D PB39C Additional Function VREF_6_10 D28 D29 D30 VREF_6_11 D31 -- -- -- VREF_5_01 -- -- PBCK0T PBCK0C -- VREF_5_02 -- -- -- VREF_5_03 -- -- -- PBCK1T PBCK1C -- -- -- -- VREF_5_04 -- -- -- VREF_5_05 -- -- -- VREF_5_06 -- -- -- VREF_4_01 -- --
Data Sheet May, 2006
Pair L17T_D1 L17C_D1 L18T_D1 L18C_D1 L19T_A0 L19C_A0 L1T_D1 L1C_D1 -- L2T_D2 L2C_D2 -- L3T_D1 L3C_D1 -- L4T_D1 L4C_D1 -- L5T_D0 L5C_D0 L6T_D0 L6C_D0 -- L7T_D1 L7C_D1 L8T_D1 L8C_D1 -- L9T_A2 L9C_A2 -- -- L10T_D0 L10C_D0 L11T_D0 L11C_D0 L12T_D1 L12C_D1 L1T_D1 L1C_D1 -- L2T_D1 L2C_D1 L3T_D1 Lattice Semiconductor
Data Sheet May, 2006
Table 67. 352-Pin PBGA Pinout BA352 AC20 AF21 AD20 AE22 L14 AF22 AD21 AE23 AC22 L15 AF23 AD22 L16 AE24 AD23 D21 AF24 M11 M12 D6 AE26 AD25 AD26 AC25 M13 AC24 AC26 M14 AB25 AB23 AB24 AB26 AA25 Y23 AA24 M15 AA26 Y25 Y26 Y24 W25 V23 W26 W24 VDDIO VREF Bank Group 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) -- -- -- -- -- -- 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 1 -- 2 2 -- 2 3 3 3 -- 3 3 -- 4 4 -- -- -- -- -- -- -- 5 5 -- 5 5 -- 6 6 -- 6 6 7 7 -- 7 7 7 7 8 8 8 8 I/O IO VDDIO4 IO IO Vss IO IO IO IO Vss IO IO Vss IO IO VDD15 VDD33 Vss Vss VDD15 VDD33 VDDIO4 IO IO Vss IO IO Vss IO IO VDDIO4 IO IO IO IO Vss IO IO IO IO IO IO IO IO OR4E02 PB23B VDDIO4 PB23C PB23D Vss PB24C PB25A PB25C PB25D Vss PB26C PB26D Vss PB27C PB27D VDD15 VDD33 Vss Vss VDD15 VDD33 VDDIO4 PR26A PR26B Vss PR25A PR25B Vss PR25C PR25D VDDIO4 PR24C PR24D PR23A PR23B Vss PR23C PR23D PR22A PR22B PR22C PR22D PR21C PR21D OR4E04 PB32D VDDIO4 PB33C PB33D Vss PB34C PB35A PB35C PB35D Vss PB36C PB36D Vss PB37C PB37D VDD15 VDD33 Vss Vss VDD15 VDD33 VDDIO4 PR38A PR38B Vss PR37A PR37B Vss PR36A PR36B VDDIO4 PR35C PR35D PR34C PR34D Vss PR33C PR33D PR32C PR32D PR31C PR31D PR30C PR30D OR4E06 PB39D VDDIO4 PB40C PB40D Vss PB42C PB43A PB44C PB44D Vss PB45C PB45D Vss PB47C PB47D VDD15 VDD33 Vss Vss VDD15 VDD33 VDDIO4 PR46C PR46D Vss PR44C PR44D Vss PR43C PR43D VDDIO4 PR41C PR41D PR40C PR40D Vss PR39C PR39D PR38C PR38D PR37C PR37D PR36C PR36D
ORCA Series 4 FPGAs
Additional Function -- -- -- VREF_4_02 -- -- -- -- VREF_4_03 -- -- -- --
PLL_CK5T/PPLL PLL_CK5C/PPLL
Pair L3C_D1 -- L4T_D1 L4C_D1 -- -- -- L5T_D1 L5C_D1 -- L6T_D1 L6C_D1 -- L7T_D0 L7C_D0 -- -- -- -- -- -- -- L8T_D0 L8C_D0 -- L9T_A1 L9C_A1 -- L10T_A1 L10C_A1 -- L11T_D0 L11C_D0 L12T_D0 L12C_D0 -- L13T_D0 L13C_D0 L14T_A1 L14C_A1 L15T_D1 L15C_D1 L16T_A1 L16C_A1 111
-- -- -- -- -- -- -- PLL_CK4T/PLL2
PLL_CK4C/PLL2
-- VREF_4_05 -- -- -- -- -- VREF_4_06 -- -- -- -- -- VREF_4_07 -- -- -- VREF_4_08 -- --
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout BA352 V25 V26 M16 U25 V24 U26 U23 T25 U24 T26 N11 R25 R26 F23 T24 P25 R23 P26 R24 N25 N23 N12 F4 N26 P24 M25 N24 N13 M26 L25 M24 L26 M23 K25 L24 K26 N14 K23 J25 K24 J26 N15 H25 H26 112 VDDIO VREF Bank Group 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 1 1 -- 1 1 -- 2 2 2 2 -- 3 3 -- 4 4 4 4 -- 5 5 -- -- 5 5 5 5 -- 6 6 6 6 -- 7 7 7 -- 7 7 8 8 -- 8 8 I/O IO IO Vss IO IO VDDIO3 IO IO IO IO Vss IO IO VDD15 IO IO IO IO VDDIO3 IO IO Vss VDD15 IO IO IO IO Vss IO IO IO IO VDDIO3 IO IO IO Vss IO IO IO IO Vss IO IO OR4E02 PR20C PR20D Vss PR19C PR19D VDDIO3 PR18C PR18D PR17A PR17B Vss PR17C PR17D VDD15 PR16C PR16D PR15A PR15B VDDIO3 PR15C PR15D Vss VDD15 PR14A PR14B PR14C PR14D Vss PR13C PR13D PR12A PR12B VDDIO3 PR12C PR12D PR11B Vss PR11C PR11D PR10C PR10D Vss PR9C PR9D OR4E04 PR29C PR29D Vss PR28C PR28D VDDIO3 PR26A PR26B PR25A PR25B Vss PR25C PR25D VDD15 PR23C PR23D PR22C PR22D VDDIO3 PR21C PR21D Vss VDD15 PR20C PR20D PR19C PR19D Vss PR17C PR17D PR16C PR16D VDDIO3 PR15A PR15B PR14B Vss PR14C PR14D PR13C PR13D Vss PR12C PR12D OR4E06 PR35C PR35D Vss PR33C PR33D VDDIO3 PR31C PR31D PR30C PR30D Vss PR29C PR29D VDD15 PR27C PR27D PR26C PR26D VDDIO3 PR25C PR25D Vss VDD15 PR24C PR24D PR23C PR23D Vss PR21C PR21D PR20C PR20D VDDIO3 PR19C PR19D PR18D Vss PR17C PR17D PR15C PR15D Vss PR14C PR14D Additional Function -- -- -- VREF_3_01 -- -- -- VREF_3_02 -- -- -- -- VREF_3_03 -- PRCK1T PRCK1C -- VREF_3_04 -- -- -- -- -- PRCK0T PRCK0C VREF_3_05 -- -- -- VREF_3_06 -- -- -- -- -- -- -- VREF_3_07 -- -- -- -- VREF_3_08 --
Data Sheet May, 2006
Pair L1T_A0 L1C_A0 -- L2T_D0 L2C_D0 -- L3T_D1 L3C_D1 L4T_D1 L4C_D1 -- L5T_A0 L5C_A0 -- L6T_D1 L6C_D1 L7T_D2 L7C_D2 -- L8T_A1 L8C_A1 -- -- L9T_D1 L9C_D1 L10T_D0 L10C_D0 -- L11T_D0 L11C_D0 L12T_D1 L12C_D1 -- L13T_D0 L13C_D0 -- -- L14T_D1 L14C_D1 L15T_D1 L15C_D1 -- L16T_A0 L16C_A0 Lattice Semiconductor
Data Sheet May, 2006
Table 67. 352-Pin PBGA Pinout BA352 L23 J24 G25 H23 G26 P12 H24 F25 G23 F26 G24 E25 E26 P13 F24 D25 E23 D26 P14 E24 C25 D24 C26 L4 P15 P16 A25 B24 A24 B23 R11 C23 A23 B22 D22 C22 A22 R12 B21 D20 C21 A21 B20 A20 VDDIO VREF Bank Group -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) -- -- -- -- -- -- 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 1 1 1 1 -- 1 1 2 2 -- 2 2 -- 3 3 3 3 -- 4 4 -- -- -- -- -- -- -- 5 5 -- 5 5 6 6 6 6 -- 7 7 -- 7 7 8 I/O VDD15 IO IO IO IO Vss IO IO IO IO VDDIO2 IO IO Vss IO IO IO IO Vss IO IO VDDIO2 VDD33 VDD15 Vss Vss VDD33 IO IO IO Vss IO IO IO IO IO IO Vss IO IO VDDIO2 IO IO IO OR4E02 VDD15 PR8C PR8D PR7A PR7B Vss PR7C PR7D PR6A PR6B VDDIO2 PR6C PR6D Vss PR5C PR5D PR4C PR4D Vss PR3C PR3D VDDIO2 VDD33 VDD15 Vss Vss VDD33 PLL_VF PT27D PT27C Vss PT26D PT26C PT26B PT26A PT25D PT25C Vss PT24D PT24C VDDIO2 PT24B PT24A PT23D OR4E04 VDD15 PR11C PR11D PR10C PR10D Vss PR9C PR9D PR7A PR7B VDDIO2 PR6A PR6B Vss PR5A PR5B PR4C PR4D Vss PR3C PR3D VDDIO2 VDD33 VDD15 Vss Vss VDD33 PLL_VF PT37D PT37C Vss PT36D PT36C PT35B PT35A PT34D PT34C Vss PT33D PT33C VDDIO2 PT32D PT32C PT31D OR4E06 VDD15 PR13C PR13D PR12C PR12D Vss PR11C PR11D PR10C PR10D VDDIO2 PR9C PR9D Vss PR7C PR7D PR5C PR5D Vss PR3C PR3D VDDIO2 VDD33 VDD15 Vss Vss VDD33 PLL_VF PT47D PT47C Vss PT45D PT45C PT43D PT43C PT42D PT42C Vss PT40D PT40C VDDIO2 PT39D PT39C PT38D
ORCA Series 4 FPGAs
Additional Function -- -- VREF_2_01 -- -- -- -- -- -- -- -- VREF_2_02 -- -- -- VREF_2_03 -- -- -- PLL_CK3T/PLL1
PLL_CK3C/PLL1
Pair -- L1T_D1 L1C_D1 L2T_D2 L2C_D2 -- L3T_D1 L3C_D1 L4T_D2 L4C_D2 -- L5T_A0 L5C_A0 -- L6T_D1 L6C_D1 L7T_D2 L7C_D2 -- L8T_D1 L8C_D1 -- -- -- -- -- -- -- L9C_A0 L9T_A0 -- L10C_A1 L10T_A1 L11C_A1 L11T_A1 L12C_A1 L12T_A1 -- L13C_D1 L13T_D1 -- L14C_D0 L14T_D0 L15C_A1 113
-- -- -- -- -- -- PLL_VF
PLL_CK2C/PPLL PLL_CK2T/PPLL
-- VREF_2_05 -- -- -- VREF_2_06 -- -- -- VREF_2_07 -- -- -- --
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout BA352 C20 R13 B19 D18 A19 C19 R15 B18 A18 B17 C18 A17 D17 R16 T11 T23 B16 C17 A16 B15 A15 C16 B14 T12 D15 A14 T4 C15 B13 D13 A13 C14 T13 B12 C13 A12 B11 T14 C12 A11 D12 B10 C11 A10 114 VDDIO VREF Bank Group 2 (TR) -- 2 (TR) 2 (TR) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- -- -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 8 -- 8 8 1 1 -- 1 1 1 1 2 2 -- -- -- 2 2 -- 3 3 3 3 -- 4 4 -- 4 4 -- 5 5 -- 5 5 5 5 -- 6 6 1 1 -- 1 I/O IO Vss IO IO IO IO Vss IO IO IO IO IO IO Vss Vss VDD15 IO IO VDDIO1 IO IO IO IO Vss IO IO VDD15 IO IO VDDIO1 IO IO Vss IO IO IO IO Vss IO IO IO IO VDDIO0 IO OR4E02 PT23C Vss PT22D PT22C PT21D PT21C Vss PT20D PT20C PT20B PT20A PT19D PT19C Vss Vss VDD15 PT18D PT18C VDDIO1 PT18B PT18A PT17D PT17C Vss PT16D PT16C VDD15 PT15D PT15C VDDIO1 PT14D PT14C Vss PT13D PT13C PT13B PT13A Vss PT12B PT12A PT11D PT11C VDDIO0 PT10D OR4E04 PT31C Vss PT29D PT29C PT28D PT28C Vss PT27D PT27C PT27B PT27A PT26D PT26C Vss Vss VDD15 PT25D PT25C VDDIO1 PT24D PT24C PT23D PT23C Vss PT21D PT21C VDD15 PT19D PT19C VDDIO1 PT18D PT18C Vss PT17D PT17C PT16D PT16C Vss PT14D PT14C PT13D PT13C VDDIO0 PT12D OR4E06 PT38C Vss PT36D PT36C PT35D PT35C Vss PT34D PT34C PT33D PT33C PT32D PT32C Vss Vss VDD15 PT30D PT30C VDDIO1 PT29D PT29C PT28D PT28C Vss PT26D PT26C VDD15 PT24D PT24C VDDIO1 PT23D PT23C Vss PT22D PT22C PT21D PT21C Vss PT19D PT19C PT18D PT18C VDDIO0 PT16D Additional Function VREF_2_08 -- -- -- -- -- -- VREF_1_01 -- -- -- -- VREF_1_02 -- -- -- -- -- -- -- VREF_1_03 -- -- -- -- -- -- -- VREF_1_04 -- PTCK1C PTCK1T -- PTCK0C PTCK0T VREF_1_05 -- -- -- VREF_1_06 MPI_RTRY_N MPI_ACK_N -- M0
Data Sheet May, 2006
Pair L15T_A1 -- L16C_D1 L16T_D1 L1C_A1 L1T_A1 -- L2C_A0 L2T_A0 L3C_D0 L3T_D0 L4C_A2 L4T_A2 -- -- -- L5C_D0 L5T_D0 -- L6C_A0 L6T_A0 L7C_D1 L7T_D1 -- L8C_D2 L8T_D2 -- L9C_D1 L9T_D1 -- L10C_D1 L10T_D1 -- L11C_D0 L11T_D0 L12C_D0 L12T_D0 -- L13C_D1 L13T_D1 L1C_D2 L1C_D2 -- L2C_A2 Lattice Semiconductor
Data Sheet May, 2006
Table 67. 352-Pin PBGA Pinout BA352 D10 AC18 B9 C10 A9 B8 A8 C9 B7 D8 A7 AC23 C8 B6 D7 A6 C7 B5 A5 AC4 C6 B4 AC8 D5 A4 C5 B3 C4 A3 AD24 AF26 B2 V4 W23 L11 L12 N16 P11 R14 T15 T16 VDDIO VREF Bank Group 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- 2 2 2 2 2 2 3 3 3 -- 4 4 4 4 -- 5 5 -- 5 5 -- 6 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O IO Vss IO IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO0 IO IO Vss IO IO Vss IO IO O IO IO VDD33 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss OR4E02 PT10C Vss PT10B PT10A PT9D PT9C PT9B PT9A PT8B PT7D PT7C Vss PT7B PT7A PT6D PT6C VDDIO0 PT5D PT5C Vss PT4D PT4C Vss PT2D PT2C PCFG_ MPI_IRQ PCCLK PDONE VDD33 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss OR4E04 PT12C Vss PT12B PT12A PT11D PT11C PT11B PT11A PT9D PT8D PT8C Vss PT7D PT7C PT6D PT6C VDDIO0 PT5D PT5C Vss PT4D PT4C Vss PT2D PT2C PCFG_ MPI_IRQ PCCLK PDONE VDD33 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss OR4E06 PT16C Vss PT15D PT15C PT14D PT14C PT13D PT13C PT11D PT10D PT10C Vss PT9D PT9C PT8D PT8C VDDIO0 PT6D PT6C Vss PT4D PT4C Vss PT2D PT2C PCFG_ MPI_IRQ PCCLK PDONE VDD33 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss
ORCA Series 4 FPGAs
Additional Function M1 -- MPI_CLK
A21/MPI_BURST_N
Pair L2T_A2 -- L3C_D0 L3C_D0 L4C_D0 L4T_D0 L5C_D1 L5T_D1 -- L6C_D2 L6T_D2 -- L7C_D2 L7T_D2 L8C_D2 L8T_D2 -- L9C_A0 L9T_A0 -- L10C_D2 L10T_D2 -- L11C_D2 L11T_D2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
M2 M3 VREF_0_02 MPI_TEA_N VREF_0_03 D0 TMS --
A20/MPI_BDIP_N
A19/MPI_TSZ1 A18/MPI_TSZ0 D3 -- D1 D2 -- TDI TCK --
PLL_CK1C/PPLL PLL_CK1T/PPLL
CFG_IRQ_N/ MPI_IRQ_N CCLK DONE -- -- -- -- -- -- -- -- -- -- -- -- --
Lattice Semiconductor
115
ORCA Series 4 FPGAs
416-Pin BGAM Pinout
Table 68. 416-Pin BGAM Pinout BM416 A2 D4 D3 A1 C1 E4 F4 C2 D2 E3 A25 D1 E2 F3 E1 F2 B1 G4 H4 G3 F1 G2 H2 H3 G1 H1 J4 K4 A26 J3 J2 J1 K2 K1 K3 L3 U16 L4 M4 L2 L1 116 VDDIO Bank -- -- -- -- -- -- -- 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) VREF Group -- -- -- -- -- -- -- -- 7 7 -- 7 7 7 8 8 -- 9 9 -- 9 9 9 9 10 10 10 10 -- 10 10 1 1 -- 1 1 -- 2 2 -- 2 I/O Vss VDD33 O VDD15 I I OR4E02 OR4E04 Vss VDD33 PRD_DATA VDD15 PRESET_N PRD_CFG_N PPRGRM_N VDDIO0 PL2D PL2C Vss PL3C PL4D PL4C PL5D PL5C Vss PL6D PL6C VDDIO0 PL7D PL7C PL8D PL8C PL9D PL9C PL10D PL10C VDD15 PL11D PL11C PL12D PL12C VDDIO7 PL13D PL13C Vss PL14D PL14C VDDIO7 PL15D Additional Function -- -- RD_DATA/TDO -- RESET_N RD_CFG_N PRGRM_N -- PLL_CK0C/HPPLL PLL_CK0T/HPPLL -- VREF_0_07 D5 D6 HDC LDC_N -- TESTCFG D7 -- VREF_0_09 A17/PPC_A31 CS0_N CS1 -- -- INIT_N DOUT -- VREF_0_10 A16/PPC_A30 A15/PPC_A29 A14/PPC_A28 -- VREF_7_01 D4 -- RDY/BUSY_N/ RCLK VREF_7_02 -- A13/PPC_A27
Data Sheet May, 2006
Pair -- -- -- -- -- -- -- -- L14C_D0 L14T_D0 -- -- L15C_D0 L15T_D0 L16C_D0 L16T_D0 -- L17C_A0 L17T_A0 -- L18C_D0 L18T_D0 L19C_A0 L19T_A0 L20C_A0 L20T_A0 L21C_A0 L21T_A0 -- L22C_A0 L22T_A0 L1C_D0 L1T_D0 -- L2C_A0 L2T_A0 -- L3C_A0 L3T_A0 -- L4C_A0
Vss VDD33 PRD_DATA VDD15 PRESET_N PRD_CFG_ N I PPRGRM_N VDDIO0 VDDIO0 IO PL2D IO PL2C Vss Vss IO PL2A IO PL3D IO PL3C IO PL4D IO PL4C Vss Vss IO PL5D IO PL5C VDDIO0 VDDIO0 IO PL5B IO PL5A IO PL6D IO PL6C IO PL6B IO PL6A IO PL7D IO PL7C VDD15 VDD15 IO PL7B IO PL7A IO PL8D IO PL8C VDDIO7 VDDIO7 IO PL9D IO PL9C Vss Vss IO PL10D IO VDDIO7 IO PL10C VDDIO7 PL10B
Lattice Semiconductor
Data Sheet May, 2006
Table 68. 416-Pin BGAM Pinout BM416 M1 M3 M2 U17 N1 N2 U14 N3 N4 AE1 P4 P3 P2 AE26 P1 R1 AF2 R2 R3 AF1 T1 T2 AF25 T4 R4 U1 U2 T3 V1 V2 U3 AF26 W1 Y1 V4 U4 V3 W2 Y2 W3 AA1 AA2 T16 VDDIO Bank 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 6 (BL) 6 (BL) -- VREF Group 2 3 3 -- 3 3 -- 4 4 -- 4 4 -- -- 5 5 -- 5 5 -- 6 6 -- 6 6 6 6 -- 7 7 7 -- 8 8 8 8 8 8 8 8 1 1 -- I/O IO IO IO Vss IO IO VDD15 IO IO Vss IO IO VDDIO7 Vss IO IO Vss IO IO VDD15 IO IO Vss IO IO IO IO VDDIO7 IO IO IO VDD15 IO IO IO IO IO IO IO IO IO IO Vss OR4E02 PL10A PL11D PL11C Vss PL11B PL11A VDD15 PL13D PL13C Vss PL14D PL14C VDDIO7 Vss PL15D PL15C Vss PL16D PL16C VDD15 PL17D PL17C Vss PL17B PL17A PL18D PL18C VDDIO7 PL18B PL19D PL19C VDD15 PL20D PL20C PL20B PL20A PL21D PL21C PL21B PL21A PL22D PL22C Vss OR4E04 PL15C PL16D PL16C Vss PL17D PL17C VDD15 PL19D PL19C Vss PL20D PL20C VDDIO7 Vss PL21D PL21C Vss PL22D PL22C VDD15 PL24D PL24C Vss PL25D PL25C PL26D PL26C VDDIO7 PL26B PL27D PL27C VDD15 PL28D PL28C PL29D PL29C PL30D PL30C PL31D PL31C PL32D PL32C Vss
ORCA Series 4 FPGAs
Additional Function A12/PPC_A26 -- -- -- A11/PPC_A25 VREF_7_03 -- RD_N/ MPI_STRB_N VREF_7_04 -- PLCK0C PLCK0T -- -- A10/PPC_A24 A9/PPC_A23 -- A8/PPC_A22 VREF_7_05 -- PLCK1C PLCK1T -- VREF_7_06 A7/PPC_A21 A6/PPC_A20 A5/PPC_A19 -- -- WR_N/MPI_RW VREF_7_07 -- A4/PPC_A18 VREF_7_08 A3/PPC_A17 A2/PPC_A16 A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 --
Pair L4T_A0 L5C_A0 L5T_A0 -- L6C_A0 L6T_A0 -- L7C_A0 L7T_A0 -- L8C_A0 L8T_A0 -- -- L9C_A0 L9T_A0 -- L10C_A0 L10T_A0 -- L11C_A0 L11T_A0 -- L12C_A0 L12T_A0 L13C_A0 L13T_A0 -- -- L14C_D0 L14T_D0 -- L15C_A0 L15T_A0 L16C_A0 L16T_A0 L17C_D0 L17T_D0 L18C_D0 L18T_D0 L1C_A0 L1T_A0 -- 117
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout BM416 Y3 W4 Y4 AA3 AB1 AB2 AC1 T17 AC2 AB3 AD1 U10 AA4 AB4 U11 U12 AC3 AD2 R14 AE2 AD3 U15 AC4 T13 AE3 AC5 AD4 AE4 AF3 AC6 AD5 AF4 AE5 AD6 AF5 AC7 AC8 AD7 AE6 AE7 AD8 AF6 AF7 T14 118 VDDIO Bank 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) -- -- -- 6 (BL) -- -- -- -- -- -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- VREF Group 1 1 2 2 -- 3 3 -- 3 3 4 -- 4 4 -- -- -- -- -- -- -- -- -- -- 5 5 5 5 5 6 6 6 6 6 -- 7 7 7 7 7 7 8 8 -- I/O IO IO IO IO VDDIO6 IO IO Vss IO IO IO Vss IO IO Vss Vss I VDDIO6 VDD15 IO VDD33 Vss VDD33 VDD15 IO IO IO IO IO IO IO IO IO IO VDDIO6 IO IO IO IO IO IO IO IO VDD15 OR4E02 PL22B PL22A PL23D PL23C VDDIO6 PL24D PL24C Vss PL25D PL25C PL26C Vss PL27D PL27C Vss Vss PTEMP VDDIO6 VDD15 LVDS_R VDD33 Vss VDD33 VDD15 PB2A PB2C PB2D PB3C PB3D PB4A PB4B PB4C PB4D PB5B VDDIO6 PB5C PB5D PB6A PB6B PB6C PB6D PB7A PB7B VDD15 OR4E04 PL33D PL33C PL34D PL34C VDDIO6 PL35B PL35A Vss PL36B PL36A PL37A Vss PL39D PL39C Vss Vss PTEMP VDDIO6 VDD15 LVDS_R VDD33 Vss VDD33 VDD15 PB2A PB2C PB2D PB4A PB4B PB4C PB4D PB5C PB5D PB6B VDDIO6 PB6C PB6D PB7C PB7D PB8C PB8D PB9C PB9D VDD15 Additional Function D9 D10 -- VREF_6_02 -- D11 D12 -- VREF_6_03 D13 VREF_6_04 -- PLL_CK7C/HPPLL PLL_CK7T/HPPLL -- -- PTEMP -- -- LVDS_R -- -- -- -- DP2 PLL_CK6T/PPLL PLL_CK6C/PPLL VREF_6_05 DP3 -- -- VREF_6_06 D14 -- -- D15 D16 D17 D18 VREF_6_07 D19 D20 D21 --
Data Sheet May, 2006
Pair L2C_D0 L2T_D0 L3C_D0 L3T_D0 -- L4C_D0 L4T_D0 -- L5C_D0 L5T_D0 -- -- L6C_A0 L6T_A0 -- -- -- -- -- -- -- -- -- -- -- L7T_D0 L7C_D0 L8T_D0 L8C_D0 L9T_D0 L9C_D0 L10T_D0 L10C_D0 -- -- L11T_A0 L11C_A0 L12T_D0 L12C_D0 L13T_D0 L13C_D0 L14T_A0 L14C_A0 --
Lattice Semiconductor
Data Sheet May, 2006
Table 68. 416-Pin BGAM Pinout BM416 AE8 AD9 AC9 AC10 AF8 AE9 AD10 AE10 AF9 AE11 AD11 AC12 AC11 AF10 AF11 AD12 AE12 P16 AF12 AF13 R16 AD13 AE13 AF14 AC14 AC13 P17 AE14 AD14 AF15 AE15 R17 AD15 AE16 AC15 AC16 AF17 AD16 AE17 T10 T11 AF18 AE18 AD17 VDDIO Bank 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- -- 5 (BC) 5 (BC) 5 (BC) VREF Group 8 8 9 9 9 9 10 10 -- 10 10 11 11 11 11 1 1 -- 1 1 -- 2 2 -- 2 2 -- 3 3 3 3 -- 3 3 4 4 -- 4 4 -- -- 5 5 -- I/O IO IO IO IO IO IO IO IO VDDIO6 IO IO IO IO IO IO IO IO VDD15 IO IO Vss IO IO VDDIO5 IO IO VDD15 IO IO IO IO Vss IO IO IO IO VDDIO5 IO IO Vss Vss IO IO VDDIO5 OR4E02 PB7C PB7D PB8C PB8D PB9C PB9D PB10C PB10D VDDIO6 PB11C PB11D PB12A PB12B PB12C PB12D PB13A PB13B VDD15 PB13C PB13D Vss PB14C PB14D VDDIO5 PB15C PB15D VDD15 PB16C PB16D PB17A PB17B Vss PB17C PB17D PB18A PB18B VDDIO5 PB18C PB18D Vss Vss PB19C PB19D VDDIO5 OR4E04 PB10C PB10D PB11C PB11D PB12C PB12D PB13C PB13D VDDIO6 PB14C PB14D PB15C PB15D PB16C PB16D PB17C PB17D VDD15 PB18C PB18D Vss PB19C PB19D VDDIO5 PB20C PB20D VDD15 PB21C PB21D PB22C PB22D Vss PB23C PB23D PB24C PB24D VDDIO5 PB25C PB25D Vss Vss PB26C PB26D VDDIO5
ORCA Series 4 FPGAs
Additional Function VREF_6_08 D22 D23 D24 VREF_6_09 D25 D26 D27 -- VREF_6_10 D28 D29 D30 VREF_6_11 D31 -- -- -- VREF_5_01 -- -- PBCK0T PBCK0C -- VREF_5_02 -- -- -- VREF_5_03 -- -- -- PBCK1T PBCK1C -- -- -- -- VREF_5_04 -- -- -- VREF_5_05 --
Pair L15T_D0 L15C_D0 L16T_A0 L16C_A0 L17T_D0 L17C_D0 L18T_A0 L18C_A0 -- L19T_A0 L19C_A0 L20T_A0 L20C_A0 L21T_A0 L21C_A0 L1T_A0 L1C_A0 -- L2T_A0 L2C_A0 -- L3T_A0 L3C_A0 -- L4T_A0 L4C_A0 -- L5T_A0 L5C_A0 L6T_A0 L6C_A0 -- L7T_D0 L7C_D0 L8T_A0 L8C_A0 -- L9T_D0 L9C_D0 -- -- L10T_A0 L10C_A0 -- 119
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout BM416 AF19 AF20 AC18 AC17 R13 AD18 AE19 P13 AE20 AD19 AF21 AE21 AD20 AC19 AC20 AF22 P14 AE22 AD21 AF23 AE23 AF24 R10 AC21 AD22 AD23 AE24 R11 AC22 AC23 P10 AD24 R12 R15 P11 AE25 AC24 AD25 AD26 AB23 AA23 AC25 AB24 AB25 120 VDDIO Bank 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) -- -- -- -- -- -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) VREF Group 5 5 6 6 -- 1 1 -- 1 1 1 1 -- 2 2 2 -- 2 3 -- 3 3 -- 3 3 4 4 -- 4 4 -- -- -- -- -- -- -- 5 5 5 5 6 6 6 I/O IO IO IO IO VDD15 IO IO Vss IO IO IO IO VDDIO4 IO IO IO Vss IO IO VDDIO4 IO IO Vss IO IO IO IO Vss IO IO VDD15 VDD33 Vss Vss VDD15 VDD33 VDDIO4 IO IO IO IO IO IO IO OR4E02 PB20C PB20D PB21A PB21B VDD15 PB22A PB22B Vss PB22C PB22D PB23A PB23B VDDIO4 PB23C PB23D PB24A Vss PB24C PB25A VDDIO4 PB25C PB25D Vss PB26C PB26D PB27A PB27B Vss PB27C PB27D VDD15 VDD33 Vss Vss VDD15 VDD33 VDDIO4 PR26A PR26B PR25A PR25B PR25C PR25D PR24A OR4E04 PB27C PB27D PB28C PB28D VDD15 PB30C PB30D Vss PB31C PB31D PB32C PB32D VDDIO4 PB33C PB33D PB34A Vss PB34C PB35A VDDIO4 PB35C PB35D Vss PB36C PB36D PB37A PB37B Vss PB37C PB37D VDD15 VDD33 Vss Vss VDD15 VDD33 VDDIO4 PR38A PR38B PR37A PR37B PR36A PR36B PR36C Additional Function -- -- -- VREF_5_06 -- -- -- -- VREF_4_01 -- -- -- -- -- VREF_4_02 -- -- -- -- -- -- VREF_4_03 -- -- -- -- VREF_4_04 -- PLL_CK5T/PPLL PLL_CK5C/PPLL -- -- -- -- -- -- -- PLL_CK4T/PLL2 PLL_CK4C/PLL2 VREF_4_05 -- -- -- --
Data Sheet May, 2006
Pair L11T_A0 L11C_A0 L12T_A0 L12C_A0 -- L1T_D0 L1C_D0 -- L2T_D0 L2C_D0 L3T_A0 L3C_A0 -- L4T_A0 L4C_A0 -- -- -- -- -- L5T_D0 L5C_D0 -- L6T_D0 L6C_D0 L7T_D0 L7C_D0 -- L8T_A0 L8C_A0 -- -- -- -- -- -- -- L9T_A0 L9C_A0 L10T_A0 L10C_A0 L11T_D0 L11C_D0 --
Lattice Semiconductor
Data Sheet May, 2006
Table 68. 416-Pin BGAM Pinout BM416 AA24 AC26 AB26 Y24 W23 AA25 AA26 Y23 W24 P12 Y25 Y26 W25 V24 W26 V23 U23 M12 V25 U24 V26 U26 U25 T24 R23 T23 M15 T25 T26 N15 R24 R25 R26 P25 P24 P26 N26 M16 N23 P23 N16 N25 N24 M26 VDDIO Bank 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) VREF Group -- 6 6 7 7 7 7 7 7 -- 8 8 8 8 -- 1 1 -- 1 1 2 -- 2 2 2 2 -- 3 3 -- 4 4 4 4 -- 5 5 -- 5 5 -- 5 5 5 I/O VDDIO4 IO IO IO IO IO IO IO IO VDD15 IO IO IO IO VDDIO3 IO IO Vss IO IO IO VDDIO3 IO IO IO IO Vss IO IO VDD15 IO IO IO IO VDDIO3 IO IO Vss IO IO VDD15 IO IO IO OR4E02 VDDIO4 PR24C PR24D PR23A PR23B PR23C PR23D PR22A PR22B VDD15 PR22C PR22D PR21C PR21D VDDIO3 PR20C PR20D Vss PR19C PR19D PR18A VDDIO3 PR18C PR18D PR17A PR17B Vss PR17C PR17D VDD15 PR16C PR16D PR15A PR15B VDDIO3 PR15C PR15D Vss PR14A PR14B VDD15 PR14C PR14D PR13A OR4E04 VDDIO4 PR35C PR35D PR34C PR34D PR33C PR33D PR32C PR32D VDD15 PR31C PR31D PR30C PR30D VDDIO3 PR29C PR29D Vss PR28C PR28D PR27A VDDIO3 PR26A PR26B PR25A PR25B Vss PR25C PR25D VDD15 PR23C PR23D PR22C PR22D VDDIO3 PR21C PR21D Vss PR20C PR20D VDD15 PR19C PR19D PR18C
ORCA Series 4 FPGAs
Additional Function -- VREF_4_06 -- -- -- -- VREF_4_07 -- -- -- -- VREF_4_08 -- -- -- -- -- -- VREF_3_01 -- -- -- -- VREF_3_02 -- -- -- -- VREF_3_03 -- PRCK1T PRCK1C -- VREF_3_04 -- -- -- -- PRCK0T PRCK0C -- VREF_3_05 -- --
Pair -- L12T_A0 L12C_A0 L13T_D0 L13C_D0 L14T_A0 L14C_A0 L15T_D0 L15C_D0 -- L16T_A0 L16C_A0 L17T_D0 L17C_D0 -- L1T_A0 L1C_A0 -- L2T_D0 L2C_D0 -- -- L3T_D0 L3C_D0 L4T_A0 L4C_A0 -- L5T_A0 L5C_A0 -- L6T_A0 L6C_A0 L7T_D0 L7C_D0 -- L8T_A0 L8C_A0 -- L9T_A0 L9C_A0 -- L10T_A0 L10C_A0 L11T_A0 121
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout BM416 M25 M17 M24 M23 L26 L25 K26 L23 L24 K25 J26 N13 J25 K24 H26 G26 N14 K23 J23 M14 J24 H25 G25 H24 L12 F26 E26 H23 G24 G23 F25 E25 F24 L15 D26 D25 C25 D24 F23 E24 L16 C26 B25 E23 122 VDDIO Bank 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) VREF Group 5 -- 6 6 6 6 -- 7 7 7 7 -- 7 7 8 8 -- 8 8 -- 1 1 1 1 -- 1 1 2 2 -- 2 2 2 -- 3 3 3 3 3 3 -- 4 4 -- I/O IO Vss IO IO IO IO VDDIO3 IO IO IO IO Vss IO IO IO IO Vss IO IO VDD15 IO IO IO IO Vss IO IO IO IO VDDIO2 IO IO IO Vss IO IO IO IO IO IO Vss IO IO VDDIO2 OR4E02 PR13B Vss PR13C PR13D PR12A PR12B VDDIO3 PR12C PR12D PR11A PR11B Vss PR11C PR11D PR10C PR10D Vss PR9C PR9D VDD15 PR8C PR8D PR7A PR7B Vss PR7C PR7D PR6A PR6B VDDIO2 PR6C PR6D PR5A Vss PR5C PR5D PR4A PR4B PR4C PR4D Vss PR3C PR3D VDDIO2 OR4E04 PR18D Vss PR17C PR17D PR16C PR16D VDDIO3 PR15A PR15B PR14A PR14B Vss PR14C PR14D PR13C PR13D Vss PR12C PR12D VDD15 PR11C PR11D PR10C PR10D Vss PR9C PR9D PR7A PR7B VDDIO2 PR6A PR6B PR6C Vss PR5A PR5B PR4A PR4B PR4C PR4D Vss PR3C PR3D VDDIO2 Additional Function -- -- -- VREF_3_06 -- -- -- -- -- -- -- -- VREF_3_07 -- -- -- -- VREF_3_08 -- -- -- VREF_2_01 -- -- -- -- -- -- -- -- VREF_2_02 -- -- -- -- VREF_2_03 -- -- -- -- -- PLL_CK3T/PLL1 PLL_CK3C/PLL1 --
Data Sheet May, 2006
Pair L11C_A0 -- L12T_A0 L12C_A0 L13T_A0 L13C_A0 -- L14T_A0 L14C_A0 L15T_D0 L15C_D0 -- L16T_D0 L16C_D0 L17T_A0 L17C_A0 -- L18T_A0 L18C_A0 -- L1T_D0 L1C_D0 L2T_D0 L2C_D0 -- L3T_A0 L3C_A0 L4T_D0 L4C_D0 -- L5T_A0 L5C_A0 -- -- L6T_A0 L6C_A0 L7T_D0 L7C_D0 L8T_D0 L8C_D0 -- L9T_D0 L9C_D0 --
Lattice Semiconductor
Data Sheet May, 2006
Table 68. 416-Pin BGAM Pinout BM416 C24 N10 L17 M10 D23 N11 B24 D22 C23 M11 A24 B23 C22 D21 C21 A23 B22 A22 B21 D20 D19 C20 B20 C19 A21 A20 N12 B19 C18 K12 D18 D17 A19 B18 C17 A18 B17 K15 K16 A17 B16 D15 D16 C16 VDDIO Bank -- -- -- -- -- -- -- 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) VREF Group -- -- -- -- -- -- -- 5 5 -- 5 5 -- 6 6 6 6 7 7 -- 7 7 8 8 8 8 -- 1 1 -- 1 1 -- 1 1 2 2 -- -- 2 2 -- 3 3 I/O VDD33 VDD15 Vss Vss VDD33 VDD15 IO IO IO Vss IO IO VDDIO2 IO IO IO IO IO IO VDDIO2 IO IO IO IO IO IO VDD15 IO IO Vss IO IO VDDIO1 IO IO IO IO Vss Vss IO IO VDDIO1 IO IO OR4E02 VDD33 VDD15 Vss Vss VDD33 VDD15 PLL_VF PT27D PT27C Vss PT26D PT26C VDDIO2 PT26B PT26A PT25D PT25C PT24D PT24C VDDIO2 PT24B PT24A PT23D PT23C PT22D PT22C VDD15 PT21D PT21C Vss PT20D PT20C VDDIO1 PT20B PT20A PT19D PT19C Vss Vss PT18D PT18C VDDIO1 PT18B PT18A OR4E04 VDD33 VDD15 Vss Vss VDD33 VDD15 PLL_VF PT37D PT37C Vss PT36D PT36C VDDIO2 PT35B PT35A PT34D PT34C PT33D PT33C VDDIO2 PT32D PT32C PT31D PT31C PT29D PT29C VDD15 PT28D PT28C Vss PT27D PT27C VDDIO1 PT27B PT27A PT26D PT26C Vss Vss PT25D PT25C VDDIO1 PT24D PT24C
ORCA Series 4 FPGAs
Additional Function -- -- -- -- -- -- PLL_VF PLL_CK2C/PPLL PLL_CK2T/PPLL -- VREF_2_05 -- -- -- -- VREF_2_06 -- -- VREF_2_07 -- -- -- -- VREF_2_08 -- -- -- -- -- -- VREF_1_01 -- -- -- -- -- VREF_1_02 -- -- -- -- -- -- VREF_1_03
Pair -- -- -- -- -- -- -- L10C_D0 L10T_D0 -- L11C_D0 L11T_D0 -- L12C_A0 L12T_A0 L13C_D0 L13T_D0 L14C_D0 L14T_D0 -- L15C_D0 L15T_D0 L16C_D0 L16T_D0 L17C_A0 L17T_A0 -- L1C_D0 L1T_D0 -- L2C_A0 L2T_A0 -- L3C_D0 L3T_D0 L4C_D0 L4T_D0 -- -- L5C_D0 L5T_D0 -- L6C_A0 L6T_A0 123
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout BM416 A16 A15 K17 C15 C14 L13 B14 A14 D14 D13 C13 L10 B13 A13 L14 A12 B12 C12 D12 L11 B11 A11 D11 C11 A10 C10 B10 A9 B9 C9 D10 D9 A8 B8 K13 A7 A6 C8 B7 C7 B6 D7 D8 124 VDDIO Bank 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) VREF Group 3 3 -- 4 4 -- 4 4 -- 5 5 -- 5 5 -- 5 5 6 6 -- 6 6 1 1 -- 1 1 1 2 2 2 2 2 2 -- 3 3 3 3 4 4 4 4 I/O IO IO Vss IO IO VDD15 IO IO VDDIO1 IO IO Vss IO IO VDD15 IO IO IO IO Vss IO IO IO IO VDDIO0 IO IO IO IO IO IO IO IO IO VDD15 IO IO IO IO IO IO IO IO OR4E02 PT17D PT17C Vss PT16D PT16C VDD15 PT15D PT15C VDDIO1 PT14D PT14C Vss PT13D PT13C VDD15 PT13B PT13A PT12D PT12C Vss PT12B PT12A PT11D PT11C VDDIO0 PT11A PT10D PT10C PT10B PT10A PT9D PT9C PT9B PT9A VDD15 PT8B PT8A PT7D PT7C PT7B PT7A PT6D PT6C OR4E04 PT23D PT23C Vss PT21D PT21C VDD15 PT19D PT19C VDDIO1 PT18D PT18C Vss PT17D PT17C VDD15 PT16D PT16C PT15D PT15C Vss PT14D PT14C PT13D PT13C VDDIO0 PT13A PT12D PT12C PT12B PT12A PT11D PT11C PT11B PT11A VDD15 PT9D PT9C PT8D PT8C PT7D PT7C PT6D PT6C Additional Function -- -- -- -- -- -- -- VREF_1_04 -- PTCK1C PTCK1T -- PTCK0C PTCK0T -- VREF_1_05 -- -- -- -- -- VREF_1_06 MPI_RTRY_N MPI_ACK_N -- VREF_0_01 M0 M1 MPI_CLK A21/ MPI_BURST_N M2 M3 VREF_0_02 MPI_TEA_N -- VREF_0_03 -- D0 TMS A20/MPI_BDIP_N A19/MPI_TSZ1 A18/MPI_TSZ0 D3
Data Sheet May, 2006
Pair L7C_A0 L7T_A0 -- L8C_A0 L8T_A0 -- L9C_A0 L9T_A0 -- L10C_A0 L10T_A0 -- L11C_A0 L11T_A0 -- L12C_A0 L12T_A0 L13C_A0 L13T_A0 -- L14C_A0 L14T_A0 L1C_A0 L1T_A0 -- -- L2C_D0 L2T_D0 L3C_A0 L3T_A0 L4C_A0 L4T_A0 L5C_A0 L5T_A0 -- L6C_A0 L6T_A0 L7C_D0 L7T_D0 L8C_D0 L8T_D0 L9C_A0 L9T_A0
Lattice Semiconductor
Data Sheet May, 2006
Table 68. 416-Pin BGAM Pinout BM416 A5 C6 B5 B26 A4 C5 B3 A3 K10 D5 D6 B4 B2 K14 C4 C3 K11 B15 AF16 T12 T15 U13 P15 N17 M13 VDDIO Bank 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) -- -- -- -- -- -- 1 (TC) 5 (BC) -- -- -- -- -- -- VREF Group -- 5 5 -- 5 5 6 6 -- 6 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O OR4E02 OR4E04
ORCA Series 4 FPGAs
Additional Function -- D1 D2 -- TDI TCK -- VREF_0_06 -- PLL_CK1C/PPLL PLL_CK1T/PPLL
CFG_IRQ_N/ MPI_IRQ_N
Pair -- L10C_D0 L10T_D0 -- L11C_D1 L11T_D1 L12C_A0 L12T_A0 -- L13C_A0 L13T_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- --
VDDIO0 VDDIO0 VDDIO0 IO PT5D PT5D IO PT5C PT5C Vss Vss Vss IO PT4D PT4D IO PT4C PT4C IO PT3D PT3D IO PT3C PT3C Vss Vss Vss IO PT2D PT2D IO PT2C PT2C O PCFG_MPI_ PCFG_MPI_IR IRQ Q IO PCCLK PCCLK VDD15 VDD15 VDD15 IO PDONE PDONE VDD33 VDD33 VDD33 Vss Vss Vss VDDIO1 VDDIO1 VDDIO1 VDDIO5 VDDIO5 VDDIO5 Vss Vss Vss Vss Vss Vss VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15
CCLK -- DONE -- -- -- -- -- -- -- -- -- --
Lattice Semiconductor
125
ORCA Series 4 FPGAs
680-Pin PBGAM Pinout
Table 69. 680-Pin PBGAM Pinout BM680 A1 F5 E4 E3 D2 G5 D3 D1 F4 A2 F3 G4 E2 H5 E5 E1 F2 J5 F1 A18 H4 G3 H3 G2 K5 G1 J4 L5 A33 J3 H2 H1 J2 J1 K3 L4 K2 L1 K1 L2 L3 N5 126 VDDIO VREF Bank Group -- -- -- -- -- -- 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- -- -- -- -- -- -- 7 7 -- 7 7 7 7 -- 8 8 8 8 -- 8 8 9 9 9 9 9 9 -- 10 10 10 10 10 10 1 1 -- 1 1 1 1 I/O Vss VDD33 O I I I VDDIO0 IO IO Vss IO IO IO IO VDDIO0 IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO IO IO IO IO VDDIO7 IO IO IO IO OR4E02 OR4E04 OR4E06 Additional Function
Data Sheet May, 2006
Pair -- -- -- -- -- -- -- L21C_D2 L21T_D2 -- L22C_D0 L22T_D0 L23C_D2 L23T_D2 -- L24C_D0 L24T_D0 L25C_D3 L25T_D3 -- L26C_D0 L26T_D0 L27C_D0 L27T_D0 L28C_D3 L28T_D3 L29C_D1 L29T_D1 -- L30C_D0 L30T_D0 L31C_D0 L31T_D0 L32C_D1 L32T_D1 L1C_D1 L1T_D1 -- L2C_D0 L2T_D0 L3C_D1 L3T_D1
Vss Vss Vss -- VDD33 VDD33 VDD33 -- PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO PRESET_N PRESET_N PRESET_N RESET_N PRD_CFG_ PRD_CFG_ PRD_CFG_ RD_CFG_N N N N PPRGRM_N PPRGRM_N PPRGRM_N PRGRM_N VDDIO0 VDDIO0 VDDIO0 -- PLL_CK0C/HPPLL PL2D PL2D PL2D PL2C PL2C PL2C PLL_CK0T/HPPLL Vss Vss Vss -- PL2B PL3D PL3D -- PL2A PL3C PL3C VREF_0_07 PL3D PL4D PL4D D5 PL3C PL4C PL4C D6 VDDIO0 VDDIO0 VDDIO0 -- PL3B PL4B PL5D -- PL3A PL4A PL5C VREF_0_08 PL4D PL5D PL6D HDC PL4C PL5C PL6C LDC_N Vss Vss Vss -- PL4B PL5B PL7D -- PL4A PL5A PL7C -- PL5D PL6D PL8D TESTCFG PL5C PL6C PL8C D7 PL5B PL7D PL9D VREF_0_09 PL5A PL7C PL9C A17/PPC_A31 PL6D PL8D PL10D CS0_N PL6C PL8C PL10C CS1 Vss Vss Vss -- PL6B PL9D PL11D -- PL6A PL9C PL11C -- PL7D PL10D PL12D INIT_N PL7C PL10C PL12C DOUT PL7B PL11D PL13D VREF_0_10 PL7A PL11C PL13C A16/PPC_A30 PL8D PL12D PL14D A15/PPC_A29 PL8C PL12C PL14C A14/PPC_A28 VDDIO7 VDDIO7 VDDIO7 -- PL8B PL12B PL15D -- PL8A PL12A PL15C -- PL9D PL13D PL16D VREF_7_01 PL9C PL13C PL16C D4
Lattice Semiconductor
Data Sheet May, 2006
Table 69. 680-Pin PBGAM Pinout BM680 AM22 M4 M2 P5 M1 M3 N1 N4 N2 P1 AM32 P2 P3 P4 R1 R4 R2 U5 T4 AN1 V5 T1 T2 T3 R3 U4 U3 AN2 U2 V2 AN33 V3 V4 W5 W2 W3 Y1 W4 AA1 AN34 Y5 Y4 AA5 AB1 VDDIO VREF Bank Group -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 2 2 2 2 -- 2 2 3 3 -- 3 3 3 3 3 3 4 4 -- 4 4 4 4 -- 4 4 -- 5 5 -- 5 5 5 5 5 5 6 6 -- 6 6 6 6 I/O Vss IO IO IO IO VDDIO7 IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO7 IO IO Vss IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO OR4E02 Vss PL9B PL9A PL10D PL10C VDDIO7 PL10B PL10A PL11D PL11C Vss PL11B PL11A PL12D PL12C PL12B PL12A PL13D PL13C Vss PL13B PL13A PL14D PL14C VDDIO7 PL14B PL14A Vss PL15D PL15C Vss PL15B PL15A PL16D PL16C PL16B PL16A PL17D PL17C Vss PL17B PL17A PL18D PL18C OR4E04 Vss PL13B PL13A PL14D PL14C VDDIO7 PL15D PL15C PL16D PL16C Vss PL17D PL17C PL18D PL18C PL18B PL18A PL19D PL19C Vss PL19B PL19A PL20D PL20C VDDIO7 PL20B PL20A Vss PL21D PL21C Vss PL21B PL21A PL22D PL22C PL23D PL23C PL24D PL24C Vss PL25D PL25C PL26D PL26C OR4E06 Vss PL17D PL17C PL18D PL18C VDDIO7 PL19D PL19C PL20D PL20C Vss PL21D PL21C PL22D PL22C PL22B PL22A PL23D PL23C Vss PL23B PL23A PL24D PL24C VDDIO7 PL24B PL24A Vss PL25D PL25C Vss PL25B PL25A PL26D PL26C PL27D PL27C PL28D PL28C Vss PL29D PL29C PL30D PL30C
ORCA Series 4 FPGAs
Additional Function -- -- --
RDY/BUSY_N/RCLK
Pair -- L4C_A1 L4T_A1 L5C_D3 L5T_D3 -- L6C_A2 L6T_A2 L7C_D0 L7T_D0 -- L8C_A0 L8T_A0 L9C_D2 L9T_D2 L10C_A1 L10T_A1 L11C_D0 L11T_D0 -- L12C_D3 L12T_D3 L13C_A0 L13T_A0 -- L14C_A0 L14T_A0 -- L15C_A0 L15T_A0 -- L16C_A0 L16T_A0 L17C_A2 L17T_A2 L18C_D1 L18T_D1 L19C_D2 L19T_D2 -- L20C_A0 L20T_A0 L21C_D3 L21T_D3 127
VREF_7_02 -- A13/PPC_A27 A12/PPC_A26 -- -- -- A11/PPC_A25 VREF_7_03 -- -- -- --
RD_N/MPI_STRB_N
VREF_7_04 -- -- -- PLCK0C PLCK0T -- -- -- -- A10/PPC_A24 A9/PPC_A23 -- -- -- A8/PPC_A22 VREF_7_05 -- -- PLCK1C PLCK1T -- VREF_7_06 A7/PPC_A21 A6/PPC_A20 A5/PPC_A19
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout BM680 U1 AB2 AA4 AB4 AB5 AC1 AC2 AC5 W1 AD2 AD3 AE1 AE2 AD4 AE3 AF1 AF2 AB13 AF3 AF4 AE5 AG1 AK5 AG2 AF5 AG3 AG4 AB14 AH1 AH3 AH4 AG5 AL3 AH2 AJ3 AJ2 AH5 AB15 AJ4 AJ1 AK1 AK2 AB20 AJ5 128 VDDIO VREF Bank Group 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) -- 7 7 7 7 7 8 8 -- 8 8 8 8 8 8 1 1 -- 1 1 2 2 -- 2 2 3 3 -- 3 3 3 3 -- 4 4 4 4 -- 4 4 4 4 -- 4 I/O VDDIO7 IO IO IO IO IO IO IO VDDIO7 IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO6 IO IO IO IO Vss IO IO IO IO VDDIO6 IO IO IO IO Vss IO IO IO IO Vss IO OR4E02 VDDIO7 PL18B PL19D PL19C PL19B PL19A PL20D PL20C VDDIO7 PL20B PL20A PL21D PL21C PL21B PL21A PL22D PL22C Vss PL22B PL22A PL23D PL23C VDDIO6 PL23B PL23A PL24D PL24C Vss PL24B PL24A PL25D PL25C VDDIO6 PL25B PL25A PL26D PL26C Vss PL26B PL26A PL27D PL27C Vss PL27B OR4E04 VDDIO7 PL26B PL27D PL27C PL27B PL27A PL28D PL28C VDDIO7 PL29D PL29C PL30D PL30C PL31D PL31C PL32D PL32C Vss PL33D PL33C PL34D PL34C VDDIO6 PL34B PL34A PL35B PL35A Vss PL36D PL36C PL36B PL36A VDDIO6 PL37D PL38C PL37B PL37A Vss PL38B PL38A PL39D PL39C Vss PL39B OR4E06 VDDIO7 PL31D PL32D PL32C PL33D PL33C PL34D PL34C VDDIO7 PL35D PL35C PL36D PL36C PL37D PL37C PL38D PL38C Vss PL39D PL39C PL40D PL40C VDDIO6 PL41D PL41C PL42D PL42C Vss PL43D PL43C PL44D PL44C VDDIO6 PL44B PL45A PL45D PL45C Vss PL46D PL46A PL47D PL47C Vss PL47B Additional Function -- -- WR_N/MPI_RW VREF_7_07 -- -- A4/PPC_A18 VREF_7_08 -- A3/PPC_A17 A2/PPC_A16 A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 -- D9 D10 -- VREF_6_02 -- -- -- D11 D12 -- -- -- VREF_6_03 D13 -- -- -- -- VREF_6_04 -- -- --
Data Sheet May, 2006
Pair -- -- L22C_A0 L22T_A0 L23C_D3 L23T_D3 L23C_A2 L23T_A2 -- L23C_A0 L23T_A0 L24C_A0 L24T_A0 L25C_D0 L25T_D0 L1C_A0 L1T_A0 -- L2C_A0 L2T_A0 L3C_D3 L3T_D3 -- L4C_D2 L4T_D2 L5C_A0 L5T_A0 -- L6C_A1 L6T_A1 L7C_D0 L7T_D0 -- -- -- L8C_D2 L8T_D2 -- -- -- L9C_A0 L9T_A0 -- L10C_D1
PLL_CK7C/HPPLL
PLL_CK7T/HPPLL -- --
Lattice Semiconductor
Data Sheet May, 2006
Table 69. 680-Pin PBGAM Pinout BM680 AK3 AB21 AK4 AM1 AL1 AL2 AB22 AK6 AL5 AM5 AM2 AN4 AK7 AL6 AM6 AL7 AN5 AK8 AP5 AB32 AN6 AK9 AP6 AL8 AM4 AM7 AM8 AK10 AP7 AL4 AK11 AM9 AL10 AP8 AP9 AM10 AK12 AL11 AL31 AN10 AP10 AN11 AM11 AN3 VDDIO VREF Bank Group 6 (BL) -- -- 6 (BL) -- -- -- -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 4 -- -- -- -- -- -- -- 5 5 -- 5 5 5 5 5 5 6 6 -- 6 6 6 6 -- 7 7 7 7 -- 7 7 8 8 8 8 9 9 -- 9 9 9 9 -- I/O IO Vss I VDDIO6 IO VDD33 Vss VDD33 IO IO VDDIO6 IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO6 IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO6 OR4E02 PL27A Vss PTEMP VDDIO6 LVDS_R VDD33 Vss VDD33 PB2A PB2B VDDIO6 PB2C PB2D PB3A PB3B PB3C PB3D PB4A PB4B Vss PB4C PB4D PB5A PB5B VDDIO6 PB5C PB5D PB6A PB6B Vss PB6C PB6D PB7A PB7B PB7C PB7D PB8A PB8B Vss PB8C PB8D PB9A PB9B VDDIO6 OR4E04 PL39A Vss PTEMP VDDIO6 LVDS_R VDD33 Vss VDD33 PB2A PB2B VDDIO6 PB2C PB2D PB3C PB3D PB4A PB4B PB4C PB4D Vss PB5C PB5D PB6A PB6B VDDIO6 PB6C PB6D PB7C PB7D Vss PB8C PB8D PB9C PB9D PB10C PB10D PB11A PB11B Vss PB11C PB11D PB12A PB12B VDDIO6 OR4E06 PL47A Vss PTEMP VDDIO6 LVDS_R VDD33 Vss VDD33 PB2A PB2B VDDIO6 PB2C PB2D PB3C PB3D PB4C PB4D PB5C PB5D Vss PB6C PB6D PB7C PB7D VDDIO6 PB8C PB8D PB9C PB9D Vss PB10C PB10D PB11C PB11D PB12C PB12D PB13A PB13B Vss PB13C PB13D PB14A PB14B VDDIO6
ORCA Series 4 FPGAs
Additional Function -- -- PTEMP -- LVDS_R -- -- -- DP2 -- -- PLL_CK6T/PPLL PLL_CK6C/PPLL -- -- VREF_6_05 DP3 -- -- -- VREF_6_06 D14 -- -- -- D15 D16 D17 D18 -- VREF_6_07 D19 D20 D21 VREF_6_08 D22 -- -- -- D23 D24 -- -- --
Pair L10T_D1 -- -- -- -- -- -- -- L11T_A0 L11C_A0 -- L12T_D2 L12C_D2 L13T_A0 L13C_A0 L14T_D1 L14C_D1 L15T_D3 L15C_D3 -- L16T_D2 L16C_D2 L17T_D2 L17C_D2 -- L18T_A0 L18C_A0 L19T_D3 L19C_D3 -- L20T_D1 L20C_D1 L21T_D2 L21C_D2 L22T_D1 L22C_D1 L23T_D0 L23C_D0 -- L24T_A0 L24C_A0 L25T_A0 L25C_A0 -- 129
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout BM680 AK13 AL12 AN12 AK14 AM3 AP12 AP13 AL13 AN13 AP3 AP14 AK15 AM14 AK16 AM13 AP15 AL15 AN16 AK17 AM16 AP16 AN17 AL17 Y15 AM17 AM18 AL18 AN18 AM12 AL19 AK18 AM19 AN19 AP20 AN20 AP21 AN21 Y20 AM21 AL21 AP22 AN22 AM15 AL22 130 VDDIO VREF Bank Group 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 9 9 9 9 -- 10 10 10 10 -- 10 10 11 11 -- 11 11 1 1 1 1 2 2 -- 2 2 2 2 -- 2 2 2 2 3 3 3 3 -- 3 3 4 4 -- 4 I/O IO IO IO IO Vss IO IO IO IO VDDIO6 IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO5 IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO5 IO OR4E02 PB9C PB9D PB10A PB10B Vss PB10C PB10D PB11A PB11B VDDIO6 PB11C PB11D PB12A PB12B Vss PB12C PB12D PB13A PB13B PB13C PB13D PB14A PB14B Vss PB14C PB14D PB15A PB15B VDDIO5 PB15C PB15D PB16A PB16B PB16C PB16D PB17A PB17B Vss PB17C PB17D PB18A PB18B VDDIO5 PB18C OR4E04 PB12C PB12D PB13A PB13B Vss PB13C PB13D PB14A PB14B VDDIO6 PB14C PB14D PB15C PB15D Vss PB16C PB16D PB17C PB17D PB18C PB18D PB19A PB19B Vss PB19C PB19D PB20A PB20B VDDIO5 PB20C PB20D PB21A PB21B PB21C PB21D PB22C PB22D Vss PB23C PB23D PB24C PB24D VDDIO5 PB25C OR4E06 PB14C PB14D PB15C PB15D Vss PB16C PB16D PB17C PB17D VDDIO6 PB18C PB18D PB19C PB19D Vss PB20C PB20D PB21C PB21D PB22C PB22D PB23A PB23B Vss PB23C PB23D PB24A PB24B VDDIO5 PB24C PB24D PB25C PB25D PB26C PB26D PB27C PB27D Vss PB28C PB28D PB29C PB29D VDDIO5 PB30C Additional Function VREF_6_09 D25 -- -- -- D26 D27 -- -- -- VREF_6_10 D28 D29 D30 -- VREF_6_11 D31 -- -- VREF_5_01 -- -- -- -- PBCK0T PBCK0C -- -- -- VREF_5_02 -- -- -- -- VREF_5_03 -- -- -- PBCK1T PBCK1C -- -- -- --
Data Sheet May, 2006
Pair L26T_D0 L26C_D0 L27T_D2 L27C_D2 -- L28T_A0 L28C_A0 L29T_A1 L29C_A1 -- L30T_D3 L30C_D3 L31T_D1 L31C_D1 -- L32T_A2 L32C_A2 L1T_D2 L1C_D2 L2T_A1 L2C_A1 L3T_A1 L3C_A1 -- L4T_A0 L4C_A0 L5T_A1 L5C_A1 -- L6T_D0 L6C_D0 L7T_A0 L7C_A0 L8T_A0 L8C_A0 L9T_A0 L9C_A0 -- L10T_A0 L10C_A0 L11T_A0 L11C_A0 -- L12T_A0
Lattice Semiconductor
Data Sheet May, 2006
Table 69. 680-Pin PBGAM Pinout BM680 AL23 Y21 AK22 AN23 Y22 AP23 AK23 AN24 AM24 AM20 AL24 AP25 AK24 AP26 AL25 AM25 AP27 AN27 V16 AK25 AL26 AM27 AK26 AK30 AP28 AN28 AL27 AL28 V17 AK27 AM28 AN29 AL32 AK28 AM29 AL29 AP29 V18 AP30 AN30 AK29 AM30 V19 AL30 VDDIO VREF Bank Group 5 (BC) -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 -- 4 4 -- 5 5 5 5 -- 5 5 6 6 6 6 1 1 -- 1 1 1 1 -- 2 2 2 2 -- 2 3 3 -- 3 3 3 3 -- 3 3 4 4 -- 4 I/O IO Vss IO IO Vss IO IO IO IO VDDIO5 IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO4 IO IO IO IO Vss IO IO IO VDDIO4 IO IO IO IO Vss IO IO IO IO Vss IO OR4E02 PB18D Vss PB19A PB19B Vss PB19C PB19D PB20A PB20B VDDIO5 PB20C PB20D PB21A PB21B PB21C PB21D PB22A PB22B Vss PB22C PB22D PB23A PB23B VDDIO4 PB23C PB23D PB24A PB24B Vss PB24C PB25A PB25B VDDIO4 PB25C PB25D PB26A PB26B Vss PB26C PB26D PB27A PB27B Vss PB27C OR4E04 PB25D Vss PB26A PB26B Vss PB26C PB26D PB27A PB27B VDDIO5 PB27C PB27D PB28C PB28D PB29C PB29D PB30C PB30D Vss PB31C PB31D PB32C PB32D VDDIO4 PB33C PB33D PB34A PB34B Vss PB34C PB35A PB35B VDDIO4 PB35C PB35D PB36A PB36B Vss PB36C PB36D PB37A PB37B Vss PB37C OR4E06 PB30D Vss PB31C PB31D Vss PB32C PB32D PB33C PB33D VDDIO5 PB34C PB34D PB35C PB35D PB36C PB36D PB37C PB37D Vss PB38C PB38D PB39C PB39D VDDIO4 PB40C PB40D PB41C PB41D Vss PB42C PB43A PB43D VDDIO4 PB44C PB44D PB45A PB45B Vss PB45C PB45D PB46C PB46D Vss PB47C
ORCA Series 4 FPGAs
Additional Function VREF_5_04 -- -- -- -- -- VREF_5_05 -- -- -- -- -- -- VREF_5_06 -- -- -- -- -- VREF_4_01 -- -- -- -- -- VREF_4_02 -- -- -- -- -- -- -- -- VREF_4_03 -- -- -- -- -- -- VREF_4_04 -- PLL_CK5T/PPLL
Pair L12C_A0 -- L13T_D2 L13C_D2 -- L14T_A3 L14C_A3 L15T_A0 L15C_A0 -- L16T_D2 L16T_D2 L17T_D3 L17C_D3 L18T_A0 L18C_A0 L1T_A0 L1C_A0 -- L2T_D0 L2C_D0 L3T_D1 L3C_D1 -- L4T_A0 L4C_A0 L5T_A0 L5C_A0 -- -- -- -- -- L6T_D1 L6C_D1 L7T_A2 L7C_A2 -- L8T_A0 L8C_A0 L9T_D1 L9C_D1 -- L10T_D2 131
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout BM680 AP31 AN31 V34 W16 AK31 AM31 AJ30 AK32 W17 AL33 AH30 AL34 AJ31 W18 AJ32 AH31 AK33 AG30 AM34 AK34 AJ33 AJ34 AG31 W19 AG32 AH33 AH34 AF31 AG33 AE31 AG34 AF33 Y13 AD30 AF34 AE32 AC30 L34 AE33 AC31 AD31 AE34 R21 AD32 132 VDDIO VREF Bank Group 4 (BR) -- -- -- -- 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 4 (BR) -- 4 (BR) 4 (BR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 4 -- -- -- -- -- 5 5 -- 5 5 5 5 -- 6 6 6 6 -- 6 6 7 7 -- 7 7 7 7 8 8 8 8 -- 8 8 1 1 -- 1 1 1 1 -- 1 I/O IO VDD33 Vss Vss VDD33 VDDIO4 IO IO Vss IO IO IO IO Vss IO IO IO IO VDDIO4 IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO3 IO IO IO IO Vss IO OR4E02 PB27D VDD33 Vss Vss VDD33 VDDIO4 PR26A PR26B Vss PR26C PR26D PR25A PR25B Vss PR25C PR25D PR24A PR24B VDDIO4 PR24C PR24D PR23A PR23B Vss PR23C PR23D PR22A PR22B PR22C PR22D PR21A PR21B Vss PR21C PR21D PR20A PR20B VDDIO3 PR20C PR20D PR19A PR19B Vss PR19C OR4E04 PB37D VDD33 Vss Vss VDD33 VDDIO4 PR38A PR38B Vss PR38C PR38D PR37A PR37B Vss PR36A PR36B PR36C PR36D VDDIO4 PR35C PR35D PR34C PR34D Vss PR33C PR33D PR32C PR32D PR31C PR31D PR30A PR30B Vss PR30C PR30D PR29A PR29B VDDIO3 PR29C PR29D PR28A PR28B Vss PR28C OR4E06 PB47D VDD33 Vss Vss VDD33 VDDIO4 PR46C PR46D Vss PR45C PR45D PR44C PR44D Vss PR43C PR43D PR42C PR42D VDDIO4 PR41C PR41D PR40C PR40D Vss PR39C PR39D PR38C PR38D PR37C PR37D PR36A PR36B Vss PR36C PR36D PR35C PR35D VDDIO3 PR34C PR34D PR34A PR33B Vss PR33C Additional Function
Data Sheet May, 2006
Pair L10C_D2 -- -- -- -- -- L11T_D1 L11C_D1 -- L12T_D2 L12C_D2 L13T_D2 L13C_D2 -- L14T_D0 L14C_D0 L15T_D2 L15C_D2 -- L16T_D0 L16C_D0 L17T_D2 L17C_D2 -- L18T_D0 L18C_D0 L19T_D2 L19C_D2 L20T_D1 L20C_D1 L22T_D0 L22C_D0 -- L21T_D3 L21C_D3 L1T_D1 L1C_D1 -- L2T_D1 L2C_D1 -- -- -- L3T_D1
PLL_CK5C/PPLL -- -- -- -- -- PLL_CK4T/PLL2 PLL_CK4C/PLL2 -- -- -- VREF_4_05 -- -- -- -- -- -- -- VREF_4_06 -- -- -- -- -- VREF_4_07 -- -- -- VREF_4_08 -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_3_01
Lattice Semiconductor
Data Sheet May, 2006
Table 69. 680-Pin PBGAM Pinout BM680 AB30 AB31 AA30 M32 AC33 AB33 AA32 Y30 R22 AB34 W30 AA33 W31 Y34 W33 V30 V31 R32 V33 V32 T16 T34 U31 T32 T31 R31 R34 T17 P34 P32 P31 P33 U34 N33 N31 M31 M33 T18 M34 L32 L33 L31 W34 K34 VDDIO VREF Bank Group 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 1 2 2 -- 2 2 2 2 -- 3 3 3 3 4 4 4 4 -- 5 5 -- 5 5 5 5 5 5 -- 6 6 6 6 -- 7 7 7 7 -- 7 7 8 8 -- 8 I/O IO IO IO VDDIO3 IO IO IO IO Vss IO IO IO IO IO IO IO IO VDDIO3 IO IO Vss IO IO IO IO IO IO Vss IO IO IO IO VDDIO3 IO IO IO IO Vss IO IO IO IO VDDIO3 IO OR4E02 PR19D PR18A PR18B VDDIO3 PR18C PR18D PR17A PR17B Vss PR17C PR17D PR16A PR16B PR16C PR16D PR15A PR15B VDDIO3 PR15C PR15D Vss PR14A PR14B PR14C PR14D PR13A PR13B Vss PR13C PR13D PR12A PR12B VDDIO3 PR12C PR12D PR11A PR11B Vss PR11C PR11D PR10A PR10B VDDIO3 PR10C OR4E04 PR28D PR27A PR27B VDDIO3 PR26A PR26B PR25A PR25B Vss PR25C PR25D PR24C PR24D PR23C PR23D PR22C PR22D VDDIO3 PR21C PR21D Vss PR20C PR20D PR19C PR19D PR18C PR18D Vss PR17C PR17D PR16C PR16D VDDIO3 PR15A PR15B PR14A PR14B Vss PR14C PR14D PR13A PR13B VDDIO3 PR13C OR4E06 PR33D PR32C PR32D VDDIO3 PR31C PR31D PR30C PR30D Vss PR29C PR29D PR28C PR28D PR27C PR27D PR26C PR26D VDDIO3 PR25C PR25D Vss PR24C PR24D PR23C PR23D PR22C PR22D Vss PR21C PR21D PR20C PR20D VDDIO3 PR19C PR19D PR18C PR18D Vss PR17C PR17D PR15A PR16D VDDIO3 PR15C
ORCA Series 4 FPGAs
Additional Function -- -- -- -- -- VREF_3_02 -- -- -- -- VREF_3_03 -- -- PRCK1T PRCK1C -- VREF_3_04 -- -- -- -- PRCK0T PRCK0C VREF_3_05 -- -- -- -- -- VREF_3_06 -- -- -- -- -- -- -- -- VREF_3_07 -- -- -- -- --
Pair L3C_D1 L4T_D0 L4C_D0 -- L5T_A0 L5C_A0 L6T_D1 L6C_D1 -- L7T_D3 L7C_D3 L8T_D1 L8C_D1 L9T_D0 L9C_D0 L10T_A0 L10C_A0 -- L11T_A0 L11C_A0 -- L13T_D2 L13C_D2 L14T_A0 L14C_A0 L15T_D1 L15C_D1 -- L16T_A1 L16C_A1 L17T_A1 L17C_A1 -- L18T_A1 L18C_A1 L19T_A1 L19C_A1 -- L20T_D1 L20C_D1 -- -- -- L21T_A0 133
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout BM680 K33 K32 T19 N30 K31 H34 J34 J33 J31 J32 G34 N32 H33 H32 H31 G33 A32 F33 G32 K30 G31 P13 E34 J30 F32 F31 B32 E33 D33 H30 E32 P14 E31 G30 C31 F30 P15 P20 E29 D30 C30 B31 P21 E28 134 VDDIO VREF Bank Group 3 (CR) 3 (CR) -- 3 (CR) 3 (CR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) -- -- -- -- -- 2 (TR) 2 (TR) -- 2 (TR) 8 8 -- 8 8 1 1 1 1 1 1 -- 1 1 2 2 -- 2 2 2 2 -- 3 3 3 3 -- 3 3 4 4 -- 4 4 -- -- -- -- -- -- 5 5 -- 5 I/O IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO2 IO IO IO IO Vss IO IO IO IO VDDIO2 IO IO IO IO Vss IO IO VDDIO2 VDD33 Vss Vss VDD33 IO IO IO Vss IO OR4E02 PR10D PR9A Vss PR9C PR9D PR8A PR8B PR8C PR8D PR7A PR7B Vss PR7C PR7D PR6A PR6B VDDIO2 PR6C PR6D PR5A PR5B Vss PR5C PR5D PR4A PR4B VDDIO2 PR4C PR4D PR3A PR3B Vss PR3C PR3D VDDIO2 VDD33 Vss Vss VDD33 PLL_VF PT27D PT27C Vss PT27B OR4E04 PR13D PR12A Vss PR12C PR12D PR11A PR11B PR11C PR11D PR10C PR10D Vss PR9C PR9D PR7A PR7B VDDIO2 PR6A PR6B PR6C PR6D Vss PR5A PR5B PR4A PR4B VDDIO2 PR4C PR4D PR3A PR3B Vss PR3C PR3D VDDIO2 VDD33 Vss Vss VDD33 PLL_VF PT37D PT37C Vss PT37B OR4E06 PR15D PR14A Vss PR14C PR14D PR13A PR13B PR13C PR13D PR12C PR12D Vss PR11C PR11D PR10C PR10D VDDIO2 PR9C PR9D PR8C PR8D Vss PR7C PR7D PR6C PR6D VDDIO2 PR5C PR5D PR4C PR4D Vss PR3C PR3D VDDIO2 VDD33 Vss Vss VDD33 PLL_VF PT47D PT47C Vss PT46D Additional Function
Data Sheet May, 2006
Pair L21C_A0 -- -- L22T_D2 L22C_D2 L1T_A0 L1C_A0 L2T_A1 L2C_A1 L3T_D1 L3C_D1 -- L4T_A0 L4C_A0 L5T_D1 L5C_D1 -- L6T_D0 L6C_D0 L7T_D2 L7C_D2 -- L8T_D2 L8C_D2 L9T_A0 L9C_A0 -- L10T_A0 L10C_A0 L11T_D2 L11C_D2 -- L12T_A0 L12C_A0 -- -- -- -- -- -- L13C_D0 L13T_D0 -- L14C_D2
-- -- -- VREF_3_08 -- -- -- -- VREF_2_01 -- -- -- -- -- -- -- -- VREF_2_02 -- -- -- -- -- VREF_2_03 -- -- -- -- -- -- VREF_2_04 -- PLL_CK3T/PLL1 PLL_CK3C/PLL1 -- -- -- -- -- PLL_VF PLL_CK2C/PPLL PLL_CK2T/PPLL -- --
Lattice Semiconductor
Data Sheet May, 2006
Table 69. 680-Pin PBGAM Pinout BM680 B30 D29 A31 C33 E27 C29 A30 E26 P22 A29 D27 C28 C27 C34 B28 E25 A28 D26 R13 C26 B27 D25 A27 B26 A26 C25 E24 C22 A25 D24 D23 B25 A11 C24 E23 B24 D22 C32 E22 D21 D4 B23 B22 A17 VDDIO VREF Bank Group 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) -- 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 5 5 5 -- 6 6 6 6 -- 7 7 7 7 -- 7 7 8 8 -- 8 8 8 8 8 8 1 1 -- 1 1 1 1 -- 1 1 2 2 -- 2 2 -- 2 2 -- I/O IO IO IO VDDIO2 IO IO IO IO Vss IO IO IO IO VDDIO2 IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO1 IO IO IO IO Vss IO IO Vss IO IO VDDIO1 OR4E02 PT27A PT26D PT26C VDDIO2 PT26B PT26A PT25D PT25C Vss PT25B PT25A PT24D PT24C VDDIO2 PT24B PT24A PT23D PT23C Vss PT23B PT23A PT22D PT22C PT22B PT22A PT21D PT21C Vss PT21B PT21A PT20D PT20C VDDIO1 PT20B PT20A PT19D PT19C Vss PT19B PT19A Vss PT18D PT18C VDDIO1 OR4E04 PT37A PT36D PT36C VDDIO2 PT35B PT35A PT34D PT34C Vss PT34B PT34A PT33D PT33C VDDIO2 PT32D PT32C PT31D PT31C Vss PT30D PT30A PT29D PT29C PT29B PT29A PT28D PT28C Vss PT28B PT28A PT27D PT27C VDDIO1 PT27B PT27A PT26D PT26C Vss PT26B PT26A Vss PT25D PT25C VDDIO1 OR4E06 PT46C PT45D PT45C VDDIO2 PT43D PT43C PT42D PT42C Vss PT41D PT41C PT40D PT40C VDDIO2 PT39D PT39C PT38D PT38C Vss PT37D PT37A PT36D PT36C PT36B PT36A PT35D PT35C Vss PT35B PT35A PT34D PT34C VDDIO1 PT33D PT33C PT32D PT32C Vss PT31D PT31C Vss PT30D PT30C VDDIO1
ORCA Series 4 FPGAs
Additional Function -- VREF_2_05 -- -- -- -- VREF_2_06 -- -- -- -- -- VREF_2_07 -- -- -- -- VREF_2_08 -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_01 -- -- -- -- -- VREF_1_02 -- -- -- -- -- -- --
Pair L14T_D2 L15C_D2 L15T_D2 -- L17C_D1 L17T_D1 L18C_D3 L18T_D3 -- L19C_D2 L19T_D2 L20C_A0 L20T_A0 -- L21C_D2 L21T_D2 L22C_D2 L22T_D2 -- -- -- L23C_D2 L23T_D2 L24C_A0 L24T_A0 L1C_D1 L1T_D1 -- L2C_D2 L2T_D2 L3C_D1 L3T_D1 -- L4C_D1 L4T_D1 L5C_D1 L5T_D1 -- L6C_D0 L6T_D0 -- L7C_A0 L7T_A0 -- 135
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout BM680 A23 C21 D20 A22 D31 A21 B21 B20 A20 B19 C19 E19 D18 A19 C18 B18 B17 C17 N3 A16 D17 B16 C16 E18 A15 D15 A14 N13 E17 A13 E16 D14 A3 C14 D13 A12 B12 A34 E15 B11 C11 E14 B3 D12 136 VDDIO VREF Bank Group 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 3 3 3 3 -- 3 3 4 4 4 4 4 4 -- 4 4 5 5 -- 5 5 5 5 5 5 6 6 -- 6 6 1 1 -- 1 1 1 1 -- 2 2 2 2 -- 2 I/O IO IO IO IO Vss IO IO IO IO IO IO IO IO VDDIO1 IO IO IO IO Vss IO IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO0 IO IO IO IO Vss IO IO IO IO VDDIO0 IO OR4E02 PT18B PT18A PT17D PT17C Vss PT17B PT17A PT16D PT16C PT16B PT16A PT15D PT15C VDDIO1 PT15B PT15A PT14D PT14C Vss PT14B PT14A PT13D PT13C PT13B PT13A PT12D PT12C Vss PT12B PT12A PT11D PT11C VDDIO0 PT11B PT11A PT10D PT10C Vss PT10B PT10A PT9D PT9C VDDIO0 PT9B OR4E04 PT24D PT24C PT23D PT23C Vss PT22D PT22C PT21D PT21C PT20D PT20C PT19D PT19C VDDIO1 PT19B PT19A PT18D PT18C Vss PT18B PT18A PT17D PT17C PT16D PT16C PT15D PT15C Vss PT14D PT14C PT13D PT13C VDDIO0 PT13B PT13A PT12D PT12C Vss PT12B PT12A PT11D PT11C VDDIO0 PT11B OR4E06 PT29D PT29C PT28D PT28C Vss PT27D PT27C PT26D PT26C PT25D PT25C PT24D PT24C VDDIO1 PT24B PT24A PT23D PT23C Vss PT23B PT23A PT22D PT22C PT21D PT21C PT20D PT20C Vss PT19D PT19C PT18D PT18C VDDIO0 PT17D PT17C PT16D PT16C Vss PT15D PT15C PT14D PT14C VDDIO0 PT13D Additional Function -- VREF_1_03 -- -- -- -- -- -- -- -- -- -- VREF_1_04 -- -- -- PTCK1C PTCK1T -- -- -- PTCK0C PTCK0T VREF_1_05 -- -- -- -- -- VREF_1_06 MPI_RTRY_N MPI_ACK_N -- -- VREF_0_01 M0 M1 -- MPI_CLK
Data Sheet May, 2006
Pair L8C_D1 L8T_D1 L9C_D2 L9T_D2 -- L10C_A0 L10T_A0 L11C_A0 L11T_A0 L12C_A0 L12T_A0 L13C_D0 L13T_D0 -- L14C_A0 L14T_A0 L15C_D0 L15T_D0 -- L16C_D2 L16T_D2 L17C_A0 L17T_A0 L18C_D3 L18T_D3 L19C_D2 L19T_D2 -- L20C_D3 L20T_D3 L1C_D1 L1T_D1 -- L2C_D0 L2T_D0 L3C_A0 L3T_A0 -- L4C_D3 L4T_D3 L5C_D2 L5T_D2 -- L6C_A0
A21/MPI_BURST_N
M2 M3 -- VREF_0_02
Lattice Semiconductor
Data Sheet May, 2006
Table 69. 680-Pin PBGAM Pinout BM680 D11 A10 B10 C9 D10 B9 A9 B1 D9 A8 B8 E12 C1 C8 D8 E11 A7 B2 A6 B7 C7 D7 C2 E10 A5 B6 E9 B33 A4 B5 D6 C6 C4 C5 E8 E7 VDDIO VREF Bank Group 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 2 3 3 3 3 3 3 -- 4 4 4 4 -- 4 4 5 5 -- 5 5 5 5 -- 5 5 6 6 -- 6 6 6 6 -- 6 6 -- I/O IO IO IO IO IO IO IO Vss IO IO IO IO VDDIO0 IO IO IO IO Vss IO IO IO IO VDDIO0 IO IO IO IO Vss IO IO IO IO VDDIO0 IO IO O IO IO VDD33 Vss VDDIO1 VDDIO5 Vss IO OR4E02 PT9A PT8D PT8C PT8B PT8A PT7D PT7C Vss PT7B PT7A PT6D PT6C VDDIO0 PT6B PT6A PT5D PT5C Vss PT5B PT5A PT4D PT4C VDDIO0 PT4B PT4A PT3D PT3C Vss PT3B PT3A PT2D PT2C VDDIO0 PT2B PT2A
PCFG_MPI_IR Q
ORCA Series 4 FPGAs
OR4E04 PT11A PT10D PT10C PT9D PT9C PT8D PT8C Vss PT7D PT7C PT6D PT6C VDDIO0 PT6B PT6A PT5D PT5C Vss PT5B PT5A PT4D PT4C VDDIO0 PT4B PT4A PT3D PT3C Vss PT3B PT3A PT2D PT2C VDDIO0 PT2B PT2A
PCFG_MPI_IR Q
OR4E06 PT13C PT12D PT12C PT11D PT11C PT10D PT10C Vss PT9D PT9C PT8D PT8C VDDIO0 PT7D PT7C PT6D PT6C Vss PT5D PT5C PT4D PT4C VDDIO0 PT4B PT4A PT3D PT3C Vss PT3B PT3A PT2D PT2C VDDIO0 PT2B PT2A
PCFG_MPI_IR Q
Additional Function MPI_TEA_N -- -- VREF_0_03 -- D0 TMS -- A20/MPI_BDIP_N A19/MPI_TSZ1 A18/MPI_TSZ0 D3 -- VREF_0_04 -- D1 D2 -- -- VREF_0_05 TDI TCK -- -- -- -- VREF_0_06 -- -- -- PLL_CK1C/PPLL PLL_CK1T/PPLL -- -- --
CFG_IRQ_N/ MPI_IRQ_N
Pair L6T_A0 L7C_A0 L7T_A0 L8C_D0 L8T_D0 L9C_A0 L9T_A0 -- L10C_D2 L10T_D2 L11C_D3 L11T_D3 -- L12C_A0 L12T_A0 L13C_D3 L13T_D3 -- L14C_D0 L14T_D0 L15C_A0 L15T_A0 -- L16C_D4 L16T_D4 L17C_D2 L17T_D2 -- L18C_D0 L18T_D0 L19C_A0 L19T_A0 -- L20C_D1 L20T_D1 -- -- -- -- -- -- -- -- -- 137
E6 -- -- B4 -- -- D5 -- -- B34 -- -- A24 1 (TC) -- AM23 5 (BC) -- AP1 -- -- K4 0 (TL) 10 Lattice Semiconductor
PCCLK PDONE VDD33 Vss VDDIO1 VDDIO5 Vss Unused
PCCLK PDONE VDD33 Vss VDDIO1 VDDIO5 Vss PL9A
PCCLK PDONE VDD33 Vss VDDIO1 VDDIO5 Vss PL11A
CCLK DONE -- -- -- -- -- --
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout BM680 M5 R5 T5 Y2 AA2 AA3 AC4 AD5 AE4 AN7 AL9 AN8 AN9 AN14 AL14 AN15 AL16 AL20 AK19 AK20 AK21 AN25 AN26 AM26 D28 B29 E21 E20 D19 B13 D16 B15 B14 C10 E13 AF30 AH32 AE30 AF32 AA31 AD33 AC34 Y31 AA34 138 VDDIO VREF Bank Group 0 (TL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 4 (BR) 2 (TR) 2 (TR) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 0 (TL) 0 (TL) 4 (BR) 4 (BR) 4 (BR) 4 (BR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 10 3 3 5 6 6 8 8 1 7 7 8 8 11 11 1 1 3 3 3 4 6 6 1 6 6 3 3 3 6 5 5 6 3 3 7 7 7 8 2 2 2 3 3 I/O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO OR4E02 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused OR4E04 PL11A PL16A PL17A PL23A PL24A PL25A PL29A PL31A PL32A PB7A PB8A PB9A PB10A PB15A PB16A PB17A PB18A PB22A PB23A PB24A PB25A PB28A PB29A PB30A PT35D PT35C PT24A PT23A PT22A PT14A PT17A PT16A PT15A PT10A PT9A PR34A PR33A PR32A PR31A PR27C PR27D PR26C PR24B PR24A OR4E06 PL13A PL20A PL21A PL27A PL28A PL29A PL35A PL37A PL38A PB9A PB10A PB11A PB12A PB19A PB20A PB21A PB22A PB27A PB28A PB29A PB30A PB35A PB36A PB37A PT44D PT44C PT29A PT28A PT27A PT19A PT22A PT21A PT20A PT12A PT11A PR40A PR39A PR38A PR37A PR31A PR32B PR30A PR29B PR28A Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Data Sheet May, 2006
Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L16C_D1 L16T_D1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Lattice Semiconductor
Data Sheet May, 2006
Table 69. 680-Pin PBGAM Pinout BM680 Y33 W32 U33 U32 T33 U30 R33 T30 R30 P30 N34 M30 L30 F34 D34 AP4 Y3 AC3 AD1 AP11 AP17 AP19 AP24 AN32 AP32 Y32 AC32 AD34 D32 E30 C12 C15 C20 C23 N16 Y16 Y17 W13 V13 U13 P18 P19 N17 N18 VDDIO VREF Bank Group 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 3 (CR) 2 (TR) 2 (TR) 2 (TR) 2 (TR) 6 (BL) 7 (CL) 7 (CL) 7 (CL) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 4 (BR) 4 (BR) 3 (CR) 3 (CR) 3 (CR) 2 (TR) 2 (TR) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- -- -- -- -- -- -- -- -- -- 4 4 5 5 5 5 5 6 6 7 7 1 1 2 3 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VDDIO7 VDDIO7 VDDIO7 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO4 VDDIO4 VDDIO3 VDDIO3 VDDIO3 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 OR4E02 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused VDDIO7 VDDIO7 VDDIO7 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO4 VDDIO4 VDDIO3 VDDIO3 VDDIO3 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 OR4E04 PR23A PR22A PR20A PR20B PR19A PR18A PR17A PR16A PR16B PR15C PR15D PR9A PR8A PR7C PR5C PB3A VDDIO7 VDDIO7 VDDIO7 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO4 VDDIO4 VDDIO3 VDDIO3 VDDIO3 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 OR4E06 PR27A PR26A PR24A PR24B PR23A PR22A PR21A PR20A PR19B PR17A PR18B PR11A PR10A PR9A PR6A PB3A VDDIO7 VDDIO7 VDDIO7 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO4 VDDIO4 VDDIO3 VDDIO3 VDDIO3 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15
ORCA Series 4 FPGAs
Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Pair -- -- L12T_A0 L12C_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 139
Lattice Semiconductor
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout BM680 N19 P16 P17 R16 R17 R18 R19 T13 T14 T15 T20 T21 T22 U14 U15 U20 U21 U22 V14 V15 V20 V21 V22 W14 W15 W20 W21 W22 Y18 Y19 AA16 AA17 AA18 AA19 AB16 AB17 AB18 AB19 C3 C13 AP2 AP18 AP33 AP34 140 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Vss Vss Vss Vss Vss Vss OR4E02 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Vss Vss Vss Vss Vss Vss OR4E04 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Vss Vss Vss Vss Vss Vss OR4E06 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Vss Vss Vss Vss Vss Vss Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Data Sheet May, 2006
Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Lattice Semiconductor
Data Sheet May, 2006
Table 69. 680-Pin PBGAM Pinout BM680 AA13 AA14 AA15 AA20 AA21 AA22 AB3 Y14 U16 U17 U18 U19 V1 R14 R15 R20 N14 N15 N20 N21 N22 AM33 VDDIO VREF Bank Group -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 (BR) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss VDDIO4 OR4E02 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss VDDIO4 OR4E04 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss VDDIO4 OR4E06 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss VDDIO4
ORCA Series 4 FPGAs
Additional Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Pair -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
PackageThermalCharacteristics Summary
Therearethreethermalparametersthatareincommonuse:JA,JC,andJC.Itshouldbenotedthatallthe parametersareaffected,tovaryingdegrees,bypackagedesign(includingpaddlesize)andchoiceofmaterials, theamountofcopperinthetestboardorsystemboard,andsystemairflow.
JA
Thisisthethermalresistancefromjunctiontoambient(theta-JA,R-theta,etc.):
JA = ------------------TJ - TA Q
whereTJisthejunctiontemperature,TA,istheambientairtemperature,andQisthechippower. Experimentally,JAisdeterminedwhenaspecialthermaltestdieisassembledintothepackageofinterest,and thepartismountedonthethermaltestboard.Thediodesonthetestchipareseparatelycalibratedinanoven.The package/boardisplacedeitherinaJEDECnaturalconvectionboxorinthewindtunnel,thelatterforforcedconvectionmeasurements.Acontrolledamountofpower(Q)isdissipatedinthetestchip'sheaterresistor,thechip's temperature(TJ)isdeterminedbytheforwarddroponthediodes,andtheambienttemperature(TA)isnoted.Note thatJAisexpressedinunitsofC/watt.
JC
ThisJEDECdesignatedparametercorrelatesthejunctiontemperaturetothecasetemperature.Itisgenerally usedtoinferthejunctiontemperaturewhilethedeviceisoperatinginthesystem.Itisnotconsideredatruethermalresistance,anditisdefinedby:
TJ - TC JC = ------------------Q
whereTCisthecasetemperatureattopdeadcenter,TJisthejunctiontemperature,andQisthechippower.DuringtheJAmeasurementsdescribedabove,besidestheotherparametersmeasured,anadditionaltemperature reading,TC,ismadewithathermocoupleattachedattop-dead-centerofthecase.JCisalsoexpressedinunitsof C/W.
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Data Sheet May, 2006
JC
ORCA Series 4 FPGAs
Thisisthethermalresistancefromjunctiontocase.Itismostoftenusedwhenattachingaheatsinktothetopof thepackage.Itisdefinedby:
JC = ------------------Q TJ - TC
Theparametersinthisequationhavebeendefinedabove.However,themeasurementsareperformedwiththe caseofthepartpressedagainstawater-cooledheatsinktodrawmostoftheheatgeneratedbythechipoutthe topofthepackage.ItisthisdifferenceinthemeasurementprocessthatdifferentiatesJCfromJC.JCisatrue thermalresistanceandisexpressedinunitsofC/W.
JB
Thisisthethermalresistancefromjunctiontoboard(JL).Itisdefinedby:
TJ - TB JB = ------------------Q
whereTBisthetemperatureoftheboardadjacenttoaleadmeasuredwithathermocouple.Theotherparameters ontheright-handsidehavebeendefinedabove.Thisisconsideredatruethermalresistance,andthemeasurementismadewithawater-cooledheatsinkpressedagainsttheboardtodrawmostoftheheatoutoftheleads. NotethatJBisexpressedinunitsofC/W,andthatthisparameterandthewayitismeasuredarestillinJEDEC committee.
Lattice Semiconductor
143
ORCA Series 4 FPGAs
Data Sheet May, 2006
PackageThermalCharacteristics
Table70.ORCASeries4PlasticPackageThermalGuidelines Package 0fpm
JA(C/W)
200fpm 500fpm
MaxPower T=70CMax TJ=125CMax 0fpm(W) 2.9 3.1 4.1
352-PinPBGA 416-pinPBGAM 680-PinPBGAM
19.0 18.0 13.4
16.0 16.5 11.5
15.0 13.5 10.5
Note: The 416-pin PBGAM and the 680-pin PBGAM packages include 2 oz. copper plates
PackageCoplanarity
Thecoplanaritylimitsofpackagesareasfollows:

PBGA: 8.0 mils PBGAM: 8.0 mils
Heat Sink Vendors for BGA Packages
In some cases the power required by the customers application is greater than the package can dissipate. Below, in alphabetical order, is a list of heat sink vendors who advertise heat sinks aimed at the BGA market. Table 71. Heat Sink Vendors Vendor Aavid Thermalloy Chip Coolers (Tyco Electronics) IERC (CTS Corp.) R-Theta Sanyo Denki Wakefield Thermal Solutions Location Concord, NH Harrisburg, PA Burbank, CA Buffalo, NY Torrance, CA Pelham, NH Phone (603) 224-9988 (800) 468-2023 (818) 842-7277 (800) 388-5428 (310) 783-5400 (603) 635-2800
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Package Parasitics
TheelectricalperformanceofanICpackage,suchassignalqualityandnoisesensitivity,isdirectlyaffectedbythe packageparasitics.Table72listseightparasiticsassociatedwiththeORCApackages.Theseparasiticsrepresent thecontributionsofallcomponentsofapackage,whichincludethebondwires,allinternalpackagerouting,and theexternalleads. FourinductancesinnHarelisted:LSWandLSL,theself-inductanceofthelead;andLMWandLML,themutualinductancetothenearestneighborlead.Theseparametersareimportantindetermininggroundbouncenoiseand inductivecrosstalknoise.ThreecapacitancesinpFarelisted:CM,themutualcapacitanceoftheleadtothenearest neighborlead;andC1andC2,thetotalcapacitanceoftheleadtoallotherleads(allotherleadsareassumedtobe grounded).Theseparametersareimportantindeterminingcapacitivecrosstalkandthecapacitiveloadingeffectof thelead.Resistancevaluesareinm. TheparasiticvaluesinTable72areforthecircuitmodelofbondwireandpackageleadparasitics.Ifthemutual capacitancevalueisnotusedinthedesigner'smodel,thenthevaluelistedasmutualcapacitanceshouldbeadded toeachoftheC1andC2capacitors. Table72.ORCASeries4PackageParasitics PackageType 352-PinPBGA 416-PinPBGAM 680-PinPBGAM LSW 5.00 3.52 3.80 LMW 2.00 0.80 1.30 RW 220 235 250 C1 1.50 0.40 0.50 C2 1.50 1.00 1.00 CM 1.50 0.25 0.30 LSL 7--12 1.5--5.0 2.8--5 LML 3--6 0.5--1.3 0.5--1.5
LSW PAD N
RW
LSL
CIRCUIT BOARD PAD
C1 LMW CM LML
C2
PAD N + 1 LSW RW C1 LSL C2
5-3862(C)r2
Figure60.PackageParasitics
Lattice Semiconductor
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ORCA Series 4 FPGAs
Data Sheet May, 2006
PackageOutlineDiagrams
TermsandDefinitions
BasicSize(BSC):Thebasicsizeofadimensionisthesizefromwhichthelimitsforthatdimensionarederivedby theapplicationoftheallowanceandthetolerance. DesignSize:Thedesignsizeofadimensionistheactualsizeofthedesign,includinganallowanceforfitandtolerance. Typical(TYP):Whenspecifiedafteradimension,thisindicatestherepeateddesignsizeifatoleranceisspecified orrepeatedbasicsizeifatoleranceisnotspecified. Reference(REF):Thereferencedimensionisanuntoleranceddimensionusedforinformationalpurposesonly.It isarepeateddimensionoronethatcanbederivedfromothervaluesinthedrawing. Minimum(MIN)orMaximum(MAX):Indicatestheminimumormaximumallowablesizeofadimension.
2725(f)
146
Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Package Outline Diagrams
352-Pin PBGA
Dimensions are in millimeters.
35.00 0.20 A1 BALL IDENTIFIER ZONE +0.70 30.00 -0.00
30.00
+0.70 -0.00 35.00 0.20
MOLD COMPOUND PWB 0.56 0.06 1.17 0.05 2.33 0.21 SEATING PLANE 0.20 0.60 0.10 SOLDER BALL 25 SPACES @ 1.27 = 31.75
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 12 14 16 18 20 22 24 26 11 13 15 17 19 21 23 25
0.75 0.15
25 SPACES @ 1.27 = 31.75
CENTER ARRAY FOR THERMAL ENHANCEMENT (OPTIONAL) (SEE NOTE BELOW) A1 BALL CORNER
5-4407(F)
Note: Although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 FPGA package.
Lattice Semiconductor
147
ORCA Series 4 FPGAs
Data Sheet May, 2006
PackageOutlineDiagrams(continued)
416-PinPBGAM
Dimensionsareinmillimeters.
27.00 PINA1 CORNER 24.00
24.00 27.00
0.610.08
1.170.05
2.280.10 SEATINGPLANE 0.20
0.500.10
SOLDERBALL 25SPACES@1.00=25.00
CORNER A1BALL
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
25 23 21 19 17 15 13 11 26 24 22 20 18 16 14 12 10 9 8 7 6 5 4 3 2 1
0.630.15
25SPACES @1.00=25.00
CENTERARRAY FORTHERMAL ENHANCEMENT
1139(F) 5-4409(F)
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Lattice Semiconductor
Data Sheet May, 2006
ORCA Series 4 FPGAs
Package Outline Drawings (continued)
680-Pin PBGAM
Dimensionsareinmillimeters.
35.00 A1 BALL IDENTIFIER ZONE 30.00 - 0.00
+ 0.70
35.00
30.00 - 0.00
+ 0.70
1.170 0.61 0.08 SEATING PLANE 0.20 0.50 0.10 SOLDER BALL 33 SPACES @ 1.00 = 33.00 2.51 MAX
AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 31 33 10 12 14 16 18 20 22 24 26 28 30 32 34
0.64 0.15
33 SPACES @ 1.00 = 33.00
A1 BALL CORNER
5-4406(F)
Lattice Semiconductor
149
ORCA Series 4 FPGAs
Data Sheet May, 2006
Ordering Information
OR4EXX Device Family OR4E02 OR4E04 OR4E06 Speed Grade Package Type BA = Plastic Ball Grid Array (PBGA) BM = Fine-Pitch Plastic Ball Grid Array (PBGAM) X XX XXX X Grade C = Commercial I = Industrial Ball Count
Table 73. Device Type Options Device OR4Exx Voltage 1.5 V internal 3.3 V/2.5 V/1.8 V/1.5 V I/O
Table 74. Recommended Temperature Range Symbol C I Description Commercial Industrial Ambient Temperature 0 C to +70 C -40 C to +85 C Junction Temperature 0 C to +85 C -40 C to +100 C
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Lattice Semiconductor
Data Sheet May, 2006
Table 75. Commercial Ordering Information Device Family OR4E02 Part Number OR4E02-3BA352C OR4E02-3BM416C OR4E02-3BM680C OR4E02-2BA352C OR4E02-2BM416C OR4E02-2BM680C OR4E02-1BA352C OR4E02-1BM416C OR4E02-1BM680C OR4E04-3BA352C OR4E04-3BM416C OR4E04-3BM680C OR4E04-2BA352C OR4E04-2BM416C OR4E04-2BM680C OR4E04-1BA352C OR4E04-1BM416C OR4E04-1BM680C OR4E06-2BA352C OR4E06-2BM680C OR4E06-1BA352C OR4E06-1BM680C Speed Grade 3 3 3 2 2 2 1 1 1 3 3 3 2 2 2 1 1 1 2 2 1 1 Package Type PBGA PBGAM PBGAM PBGA PBGAM PBGAM PBGA PBGAM PBGAM PBGA PBGAM PBGAM PBGA PBGAM PBGAM PBGA PBGAM PBGAM PBGA PBGAM PBGA PBGAM Ball Count 352 416 680 352 416 680 352 416 680 352 416 680 352 416 680 352 416 680 352 680 352 680
ORCA Series 4 FPGAs
Grade C C C C C C C C C C C C C C C C C C C C C C
OR4E04
OR4E06
Note: For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only.
Lattice Semiconductor
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ORCA Series 4 FPGAs
Table 76. Industrial Ordering Information Device Family OR4E02 Part Number OR4E02-2BA352I OR4E02-2BM416I OR4E02-2BM680I OR4E02-1BA352I OR4E02-1BM416I OR4E02-1BM680I OR4E04-2BA352I OR4E04-2BM416I OR4E04-2BM680I OR4E04-1BA352I OR4E04-1BM416I OR4E04-1BM680I OR4E06-1BA352I OR4E06-1BM680I Speed Grade 2 2 2 1 1 1 2 2 2 1 1 1 1 1 Package Type PBGA PBGAM PBGAM PBGA PBGAM PBGAM PBGA PBGAM PBGAM PBGA PBGAM PBGAM PBGA PBGAM Ball Count 352 416 680 352 416 680 352 416 680 352 416 680 352 680 Grade I I I I I I I I I I I I I I
Data Sheet May, 2006
OR4E04
OR4E06
Note: For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only.
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Lattice Semiconductor

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